// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright (c) 2007 MIPS Technologies, Inc.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
////////////////////////////////////////////////////////////////////
//
//
output header {{
#include <iostream>
- /**
- * Base class for integer operations.
- */
- class IntOp : public MipsStaticInst
+ using namespace std;
+ /**
+ * Base class for integer operations.
+ */
+ class IntOp : public MipsStaticInst
+ {
+ protected:
+ using MipsStaticInst::MipsStaticInst;
+
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
+ };
+
+
+ class HiLoOp: public IntOp
+ {
+ protected:
+ using IntOp::IntOp;
+
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
+ };
+
+ class HiLoRsSelOp: public HiLoOp
+ {
+ protected:
+ using HiLoOp::HiLoOp;
+
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
+ };
+
+ class HiLoRdSelOp: public HiLoOp
+ {
+ protected:
+ using HiLoOp::HiLoOp;
+
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
+ };
+
+ class HiLoRdSelValOp: public HiLoOp
+ {
+ protected:
+ using HiLoOp::HiLoOp;
+
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
+ };
+
+ class IntImmOp : public MipsStaticInst
+ {
+ protected:
+ int16_t imm;
+ int32_t sextImm;
+ uint32_t zextImm;
+
+ IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ MipsStaticInst(mnem, _machInst, __opClass), imm(INTIMM),
+ sextImm(INTIMM), zextImm(0x0000FFFF & INTIMM)
{
- protected:
-
- /// Constructor
- IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
- MipsStaticInst(mnem, _machInst, __opClass)
- {
- }
+ // If Bit 15 is 1 then sign extend.
+ int32_t temp = sextImm & 0x00008000;
+ if (temp > 0 && strcmp(mnemonic,"lui") != 0) {
+ sextImm |= 0xFFFF0000;
+ }
+ }
- std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- };
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
+ };
+}};
- class HiLoOp: public IntOp
- {
- protected:
+// HiLo instruction class execute method template.
+def template HiLoExecute {{
+ Fault
+ %(class_name)s::execute(
+ ExecContext *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_rd)s;
+ %(code)s;
+
+ if(fault == NoFault) {
+ %(op_wb)s;
+ }
+ return fault;
+ }
+}};
- /// Constructor
- HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
- IntOp(mnem, _machInst, __opClass)
- {
- }
+// HiLoRsSel instruction class execute method template.
+def template HiLoRsSelExecute {{
+ Fault
+ %(class_name)s::execute(
+ ExecContext *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+
+ if (ACSRC > 0 && !isDspEnabled(xc)) {
+ fault = std::make_shared<DspStateDisabledFault>();
+ } else {
+ %(op_rd)s;
+ %(code)s;
+ }
- std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- };
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+ return fault;
+ }
+}};
- class HiLoMiscOp: public HiLoOp
- {
- protected:
+// HiLoRdSel instruction class execute method template.
+def template HiLoRdSelExecute {{
+ Fault
+ %(class_name)s::execute(
+ ExecContext *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+
+ if (ACDST > 0 && !isDspEnabled(xc)) {
+ fault = std::make_shared<DspStateDisabledFault>();
+ } else {
+ %(op_rd)s;
+ %(code)s;
+ }
- /// Constructor
- HiLoMiscOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
- HiLoOp(mnem, _machInst, __opClass)
- {
- }
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+ return fault;
+ }
+}};
- std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- };
+//Outputs to decoder.cc
+output decoder {{
+ std::string
+ IntOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ // just print the first dest... if there's a second one,
+ // it's generally implicit
+ if (_numDestRegs > 0) {
+ printReg(ss, destRegIdx(0));
+ ss << ", ";
+ }
+ // just print the first two source regs... if there's
+ // a third one, it's a read-modify-write dest (Rc),
+ // e.g. for CMOVxx
+ if (_numSrcRegs > 0) {
+ printReg(ss, srcRegIdx(0));
+ }
- class IntImmOp : public MipsStaticInst
- {
- protected:
+ if (_numSrcRegs > 1) {
+ ss << ", ";
+ printReg(ss, srcRegIdx(1));
+ }
- int16_t imm;
- int32_t sextImm;
- uint32_t zextImm;
+ return ss.str();
+ }
- /// Constructor
- IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
- MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM),
- sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM)
- {
- //If Bit 15 is 1 then Sign Extend
- int32_t temp = sextImm & 0x00008000;
- if (temp > 0 && mnemonic != "lui") {
- sextImm |= 0xFFFF0000;
- }
- }
+ std::string
+ HiLoOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+ {
+ std::stringstream ss;
- std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ ccprintf(ss, "%-10s ", mnemonic);
+ // Destination Registers are implicit for HI/LO ops
+ if (_numSrcRegs > 0) {
+ printReg(ss, srcRegIdx(0));
+ }
- };
+ if (_numSrcRegs > 1) {
+ ss << ", ";
+ printReg(ss, srcRegIdx(1));
+ }
-}};
+ return ss.str();
+ }
-// HiLo<Misc> instruction class execute method template.
-// Mainly to get instruction trace data to print out
-// correctly
-def template HiLoExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
- {
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_decl)s;
- %(op_rd)s;
- %(code)s;
-
- if(fault == NoFault)
- {
- %(op_wb)s;
- //If there are 2 Destination Registers then
- //concatenate the values for the traceData
- if(traceData && _numDestRegs == 2) {
- uint64_t hilo_final_val = (uint64_t)HI << 32 | LO;
- traceData->setData(hilo_final_val);
- }
- }
- return fault;
- }
-}};
+ std::string
+ HiLoRsSelOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+ {
+ std::stringstream ss;
-//Outputs to decoder.cc
-output decoder {{
- std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- std::stringstream ss;
+ ccprintf(ss, "%-10s ", mnemonic);
- ccprintf(ss, "%-10s ", mnemonic);
+ if (_numDestRegs > 0 && destRegIdx(0).index() < 32) {
+ printReg(ss, destRegIdx(0));
+ } else if (_numSrcRegs > 0 && srcRegIdx(0).index() < 32) {
+ printReg(ss, srcRegIdx(0));
+ }
- // just print the first dest... if there's a second one,
- // it's generally implicit
- if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
- ss << ", ";
- }
+ return ss.str();
+ }
- // just print the first two source regs... if there's
- // a third one, it's a read-modify-write dest (Rc),
- // e.g. for CMOVxx
- if (_numSrcRegs > 0) {
- printReg(ss, _srcRegIdx[0]);
- }
+ std::string
+ HiLoRdSelOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+ {
+ std::stringstream ss;
- if (_numSrcRegs > 1) {
- ss << ", ";
- printReg(ss, _srcRegIdx[1]);
- }
+ ccprintf(ss, "%-10s ", mnemonic);
- return ss.str();
+ if (_numDestRegs > 0 && destRegIdx(0).index() < 32) {
+ printReg(ss, destRegIdx(0));
+ } else if (_numSrcRegs > 0 && srcRegIdx(0).index() < 32) {
+ printReg(ss, srcRegIdx(0));
}
- std::string HiLoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- std::stringstream ss;
+ return ss.str();
+ }
- ccprintf(ss, "%-10s ", mnemonic);
+ std::string
+ HiLoRdSelValOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+ {
+ std::stringstream ss;
- //Destination Registers are implicit for HI/LO ops
- if (_numSrcRegs > 0) {
- printReg(ss, _srcRegIdx[0]);
- }
-
- if (_numSrcRegs > 1) {
- ss << ", ";
- printReg(ss, _srcRegIdx[1]);
- }
+ ccprintf(ss, "%-10s ", mnemonic);
- return ss.str();
+ if (_numDestRegs > 0 && destRegIdx(0).index() < 32) {
+ printReg(ss, destRegIdx(0));
+ } else if (_numSrcRegs > 0 && srcRegIdx(0).index() < 32) {
+ printReg(ss, srcRegIdx(0));
}
- std::string HiLoMiscOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- std::stringstream ss;
+ return ss.str();
+ }
- ccprintf(ss, "%-10s ", mnemonic);
+ std::string
+ IntImmOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+ {
+ std::stringstream ss;
- if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
- printReg(ss, _destRegIdx[0]);
- } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
- printReg(ss, _srcRegIdx[0]);
- }
+ ccprintf(ss, "%-10s ", mnemonic);
- return ss.str();
+ if (_numDestRegs > 0) {
+ printReg(ss, destRegIdx(0));
}
- std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- std::stringstream ss;
-
- ccprintf(ss, "%-10s ", mnemonic);
-
- if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
- }
+ ss << ", ";
+ if (_numSrcRegs > 0) {
+ printReg(ss, srcRegIdx(0));
ss << ", ";
+ }
- if (_numSrcRegs > 0) {
- printReg(ss, _srcRegIdx[0]);
- ss << ", ";
- }
-
- if( mnemonic == "lui")
- ccprintf(ss, "0x%x ", sextImm);
- else
- ss << (int) sextImm;
+ if(strcmp(mnemonic,"lui") == 0)
+ ccprintf(ss, "0x%x ", sextImm);
+ else
+ ss << (int) sextImm;
- return ss.str();
- }
+ return ss.str();
+ }
}};
exec_output = BasicExecute.subst(iop)
}};
-def format HiLoOp(code, *opt_flags) {{
- code += 'HI = val<63:32>;\n'
- code += 'LO = val<31:0>;\n'
-
- iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags)
+def format HiLoRsSelOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'HiLoRsSelOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
- exec_output = HiLoExecute.subst(iop)
+ exec_output = HiLoRsSelExecute.subst(iop)
}};
-def format HiLoMiscOp(code, *opt_flags) {{
- iop = InstObjParams(name, Name, 'HiLoMiscOp', code, opt_flags)
+def format HiLoRdSelOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
+ exec_output = HiLoRdSelExecute.subst(iop)
}};
+def format HiLoRdSelValOp(code, *opt_flags) {{
+ if '_sd' in code:
+ code = 'int64_t ' + code
+ elif '_ud' in code:
+ code = 'uint64_t ' + code
+ code += 'HI_RD_SEL = val<63:32>;\n'
+ code += 'LO_RD_SEL = val<31:0>;\n'
+ iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = HiLoRdSelExecute.subst(iop)
+}};
+def format HiLoOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = HiLoExecute.subst(iop)
+}};
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