// -*- mode:c++ -*-
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
////////////////////////////////////////////////////////////////////
//
// Integer operate instructions
//
-
-//Outputs to decoder.hh
output header {{
#include <iostream>
using namespace std;
- /**
- * Base class for integer operations.
- */
- class IntOp : public MipsStaticInst
- {
- protected:
+ /**
+ * Base class for integer operations.
+ */
+ class IntOp : public MipsStaticInst
+ {
+ protected:
+ using MipsStaticInst::MipsStaticInst;
+
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
+ };
+
+
+ class HiLoOp: public IntOp
+ {
+ protected:
+ using IntOp::IntOp;
+
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
+ };
+
+ class HiLoRsSelOp: public HiLoOp
+ {
+ protected:
+ using HiLoOp::HiLoOp;
- /// Constructor
- IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
- MipsStaticInst(mnem, _machInst, __opClass)
- {
- }
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
+ };
- std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- };
+ class HiLoRdSelOp: public HiLoOp
+ {
+ protected:
+ using HiLoOp::HiLoOp;
- class IntImmOp : public MipsStaticInst
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
+ };
+
+ class HiLoRdSelValOp: public HiLoOp
+ {
+ protected:
+ using HiLoOp::HiLoOp;
+
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
+ };
+
+ class IntImmOp : public MipsStaticInst
+ {
+ protected:
+ int16_t imm;
+ int32_t sextImm;
+ uint32_t zextImm;
+
+ IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ MipsStaticInst(mnem, _machInst, __opClass), imm(INTIMM),
+ sextImm(INTIMM), zextImm(0x0000FFFF & INTIMM)
{
- protected:
+ // If Bit 15 is 1 then sign extend.
+ int32_t temp = sextImm & 0x00008000;
+ if (temp > 0 && strcmp(mnemonic,"lui") != 0) {
+ sextImm |= 0xFFFF0000;
+ }
+ }
- int16_t imm;
- int32_t sextImm;
- uint32_t zextImm;
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
+ };
- /// Constructor
- IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
- MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM),
- sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM)
- {
- //If Bit 15 is 1 then Sign Extend
- int32_t temp = sextImm & 0x00008000;
- if (temp > 0 && mnemonic != "lui") {
- sextImm |= 0xFFFF0000;
- }
- }
+}};
- std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+// HiLo instruction class execute method template.
+def template HiLoExecute {{
+ Fault
+ %(class_name)s::execute(
+ ExecContext *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_rd)s;
+ %(code)s;
- };
+ if(fault == NoFault) {
+ %(op_wb)s;
+ }
+ return fault;
+ }
+}};
+// HiLoRsSel instruction class execute method template.
+def template HiLoRsSelExecute {{
+ Fault
+ %(class_name)s::execute(
+ ExecContext *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+
+ if (ACSRC > 0 && !isDspEnabled(xc)) {
+ fault = std::make_shared<DspStateDisabledFault>();
+ } else {
+ %(op_rd)s;
+ %(code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+ return fault;
+ }
+}};
+
+// HiLoRdSel instruction class execute method template.
+def template HiLoRdSelExecute {{
+ Fault
+ %(class_name)s::execute(
+ ExecContext *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+
+ if (ACDST > 0 && !isDspEnabled(xc)) {
+ fault = std::make_shared<DspStateDisabledFault>();
+ } else {
+ %(op_rd)s;
+ %(code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+ return fault;
+ }
}};
//Outputs to decoder.cc
output decoder {{
- std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- std::stringstream ss;
+ std::string
+ IntOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+ {
+ std::stringstream ss;
- ccprintf(ss, "%-10s ", mnemonic);
+ ccprintf(ss, "%-10s ", mnemonic);
- // just print the first dest... if there's a second one,
- // it's generally implicit
- if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
- ss << ",";
- }
+ // just print the first dest... if there's a second one,
+ // it's generally implicit
+ if (_numDestRegs > 0) {
+ printReg(ss, destRegIdx(0));
+ ss << ", ";
+ }
- // just print the first two source regs... if there's
- // a third one, it's a read-modify-write dest (Rc),
- // e.g. for CMOVxx
- if (_numSrcRegs > 0) {
- printReg(ss, _srcRegIdx[0]);
- }
+ // just print the first two source regs... if there's
+ // a third one, it's a read-modify-write dest (Rc),
+ // e.g. for CMOVxx
+ if (_numSrcRegs > 0) {
+ printReg(ss, srcRegIdx(0));
+ }
- if (_numSrcRegs > 1) {
- ss << ",";
- printReg(ss, _srcRegIdx[1]);
- }
+ if (_numSrcRegs > 1) {
+ ss << ", ";
+ printReg(ss, srcRegIdx(1));
+ }
+
+ return ss.str();
+ }
+
+ std::string
+ HiLoOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+ {
+ std::stringstream ss;
- return ss.str();
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ // Destination Registers are implicit for HI/LO ops
+ if (_numSrcRegs > 0) {
+ printReg(ss, srcRegIdx(0));
}
- std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- std::stringstream ss;
+ if (_numSrcRegs > 1) {
+ ss << ", ";
+ printReg(ss, srcRegIdx(1));
+ }
- ccprintf(ss, "%-10s ", mnemonic);
+ return ss.str();
+ }
- if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
- }
+ std::string
+ HiLoRsSelOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+ {
+ std::stringstream ss;
- ss << ",";
+ ccprintf(ss, "%-10s ", mnemonic);
- if (_numSrcRegs > 0) {
- printReg(ss, _srcRegIdx[0]);
- ss << ",";
- }
+ if (_numDestRegs > 0 && destRegIdx(0).index() < 32) {
+ printReg(ss, destRegIdx(0));
+ } else if (_numSrcRegs > 0 && srcRegIdx(0).index() < 32) {
+ printReg(ss, srcRegIdx(0));
+ }
+
+ return ss.str();
+ }
+
+ std::string
+ HiLoRdSelOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ if (_numDestRegs > 0 && destRegIdx(0).index() < 32) {
+ printReg(ss, destRegIdx(0));
+ } else if (_numSrcRegs > 0 && srcRegIdx(0).index() < 32) {
+ printReg(ss, srcRegIdx(0));
+ }
+
+ return ss.str();
+ }
+
+ std::string
+ HiLoRdSelValOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ if (_numDestRegs > 0 && destRegIdx(0).index() < 32) {
+ printReg(ss, destRegIdx(0));
+ } else if (_numSrcRegs > 0 && srcRegIdx(0).index() < 32) {
+ printReg(ss, srcRegIdx(0));
+ }
+
+ return ss.str();
+ }
+
+ std::string
+ IntImmOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+ {
+ std::stringstream ss;
- if( mnemonic == "lui")
- ccprintf(ss, "%08p ", sextImm);
- else
- ss << (int) sextImm;
+ ccprintf(ss, "%-10s ", mnemonic);
- return ss.str();
+ if (_numDestRegs > 0) {
+ printReg(ss, destRegIdx(0));
}
+ ss << ", ";
+
+ if (_numSrcRegs > 0) {
+ printReg(ss, srcRegIdx(0));
+ ss << ", ";
+ }
+
+ if(strcmp(mnemonic,"lui") == 0)
+ ccprintf(ss, "0x%x ", sextImm);
+ else
+ ss << (int) sextImm;
+
+ return ss.str();
+ }
+
}};
-//Used by decoder.isa
def format IntOp(code, *opt_flags) {{
- orig_code = code
- cblk = CodeBlock(code)
-
- # Figure out if we are creating a IntImmOp or a IntOp
- # by looking at the instruction name
- iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
- strlen = len(name)
- if name[strlen-1] == 'i' or name[strlen-2:] == 'iu':
- iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
-
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = OperateNopCheckDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
+ iop = InstObjParams(name, Name, 'IntOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = RegNopCheckDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+
+def format IntImmOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'IntImmOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = ImmNopCheckDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+
+def format HiLoRsSelOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'HiLoRsSelOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = HiLoRsSelExecute.subst(iop)
+}};
+
+def format HiLoRdSelOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = HiLoRdSelExecute.subst(iop)
}};
+def format HiLoRdSelValOp(code, *opt_flags) {{
+ if '_sd' in code:
+ code = 'int64_t ' + code
+ elif '_ud' in code:
+ code = 'uint64_t ' + code
+ code += 'HI_RD_SEL = val<63:32>;\n'
+ code += 'LO_RD_SEL = val<31:0>;\n'
+
+ iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = HiLoRdSelExecute.subst(iop)
+}};
+
+def format HiLoOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = HiLoExecute.subst(iop)
+}};
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