const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
const StaticInstPtr &memAccInst() const { return memAccPtr; }
+
+ unsigned memAccFlags() { return memAccessFlags; }
};
/**
flags[IsFloating] ? FD : RD,
RS, RT);
}
+
+}};
+
+output exec {{
+ /** return data in cases where there the size of data is only
+ known in the packet
+ */
+ uint64_t getStoreData(%(CPU_exec_context)s *xc, Packet *packet) {
+ switch (packet->getSize())
+ {
+ case 8:
+ return packet->get<uint8_t>();
+
+ case 16:
+ return packet->get<uint16_t>();
+
+ case 32:
+ return packet->get<uint32_t>();
+
+ case 864:
+ return packet->get<uint64_t>();
+
+ default:
+ std::cerr << "bad store data size = " << packet->getSize() << std::endl;
+
+ assert(0);
+ return 0;
+ }
+ }
+
+
}};
def template LoadStoreDeclare {{
{
public:
/// Constructor
- EAComp(MachInst machInst);
+ EAComp(ExtMachInst machInst);
%(BasicExecDeclare)s
};
{
public:
/// Constructor
- MemAcc(MachInst machInst);
+ MemAcc(ExtMachInst machInst);
%(BasicExecDeclare)s
};
public:
/// Constructor.
- %(class_name)s(MachInst machInst);
+ %(class_name)s(ExtMachInst machInst);
%(BasicExecDeclare)s
%(InitiateAccDeclare)s
%(CompleteAccDeclare)s
+
+ %(MemAccSizeDeclare)s
};
}};
def template CompleteAccDeclare {{
- Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
+ Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
+def template MemAccSizeDeclare {{
+ int memAccSize(%(CPU_exec_context)s *xc);
+}};
def template EACompConstructor {{
/** TODO: change op_class to AddrGenOp or something (requires
* creating new member of OpClass enum in op_class.hh, updating
* config files, etc.). */
- inline %(class_name)s::EAComp::EAComp(MachInst machInst)
+ inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
{
%(constructor)s;
def template MemAccConstructor {{
- inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
+ inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
{
%(constructor)s;
def template LoadStoreConstructor {{
- inline %(class_name)s::%(class_name)s(MachInst machInst)
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
new EAComp(machInst), new MemAcc(machInst))
{
%(op_rd)s;
%(ea_code)s;
+ // NOTE: Trace Data is written using execute or completeAcc templates
if (fault == NoFault) {
- %(op_wb)s;
xc->setEA(EA);
}
Addr EA;
Fault fault = NoFault;
- %(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
+
EA = xc->getEA();
- if (fault == NoFault) {
- fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
- %(memacc_code)s;
- }
+ fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
- if (fault == NoFault) {
- %(op_wb)s;
- }
+ %(memacc_code)s;
+
+ // NOTE: Write back data using execute or completeAcc templates
return fault;
}
}
}};
-
def template LoadCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt,
+ Fault %(class_name)s::completeAcc(Packet *pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
%(fp_enable_check)s;
%(op_decl)s;
+ %(op_rd)s;
Mem = pkt->get<typeof(Mem)>();
}};
+
+def template LoadStoreMemAccSize {{
+ int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+ {
+ // Return the memory access size in bytes
+ return (%(mem_acc_size)d / 8);
+ }
+}};
+
def template StoreMemAccExecute {{
Fault
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
+
EA = xc->getEA();
if (fault == NoFault) {
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
- }
-
- if (fault == NoFault) {
- %(postacc_code)s;
- }
-
- if (fault == NoFault) {
- %(op_wb)s;
+ // @NOTE: Need to Call Complete Access to Set Trace Data
+ //if (traceData) { traceData->setData(Mem); }
}
return fault;
}
}};
-
def template StoreExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
def template StoreCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt,
+ Fault %(class_name)s::completeAcc(Packet *pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
if (fault == NoFault) {
%(op_wb)s;
+
+ if (traceData) { traceData->setData(getStoreData(xc, pkt)); }
}
return fault;
}};
def template StoreCondCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt,
+ Fault %(class_name)s::completeAcc(Packet *pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
def template MiscCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt,
+ Fault %(class_name)s::completeAcc(Packet *pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
}
}};
+
+def template MiscMemAccSize {{
+ int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+ {
+ panic("Misc instruction does not support split access method!");
+ return 0;
+ }
+}};
+
def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
decl_code += '\tbyte_offset ^= 3;\n'
decl_code += '#endif\n'
decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n'
+ #decl_code += 'xc->readFunctional(EA,(uint32_t&)mem_word);'
memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
(header_output, decoder_output, decode_block, exec_output) = \