// -*- mode:c++ -*-
-// Copyright \e.A\eN) 2007 MIPS Technologies, Inc. All Rights Reserved
-
-// This software is part of the M5 simulator.
-
-// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
-// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// TO THESE TERMS AND CONDITIONS.
-
-// Permission is granted to use, copy, create derivative works and
-// distribute this software and such derivative works for any purpose,
-// so long as (1) the copyright notice above, this grant of permission,
-// and the disclaimer below appear in all copies and derivative works
-// made, (2) the copyright notice above is augmented as appropriate to
-// reflect the addition of any new copyrightable work in a derivative
-// work (e.g., Copyright
\e.A
\eN) <Publication Year> Copyright Owner), and (3)
-// the name of MIPS Technologies, Inc. (\e$B!H\e(BMIPS\e$B!I\e(B) is not used in any
-// advertising or publicity pertaining to the use or distribution of
-// this software without specific, written prior authorization.
-
-// THIS SOFTWARE IS PROVIDED \e$B!H\e(BAS IS.\e$B!I\e(B MIPS MAKES NO WARRANTIES AND
-// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
-
-//Authors: Steven K. Reinhardt
-// Korey L. Sewell
+// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
let {{
def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
mem_flags = makeList(mem_flags)
inst_flags = makeList(inst_flags)
- # add hook to get effective addresses into execution trace output.
- ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
-
# Some CPU models execute the memory operation as an atomic unit,
# while others want to separate them into an effective address
# computation and a memory access operation. As a result, we need
iop = InstObjParams(name, Name, base_class,
{ 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code },
inst_flags)
- ea_iop = InstObjParams(name, Name, base_class,
- { 'ea_code':ea_code },
- inst_flags)
- memacc_iop = InstObjParams(name, Name, base_class,
- { 'memacc_code':memacc_code, 'postacc_code':postacc_code },
- inst_flags)
if mem_flags:
- s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
+ mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
+ s = '\n\tmemAccessFlags = ' + '|'.join(mem_flags) + ';'
iop.constructor += s
- memacc_iop.constructor += s
# select templates
# corresponding Store template..
StoreCondInitiateAcc = StoreInitiateAcc
- memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
fullExecTemplate = eval(exec_template_base + 'Execute')
initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
- eaCompExecuteTemplate = eval('EACompExecute')
-
- if (exec_template_base == 'Load' or exec_template_base == 'Store'):
- memAccSizeTemplate = eval('LoadStoreMemAccSize')
- else:
- memAccSizeTemplate = eval('MiscMemAccSize')
# (header_output, decoder_output, decode_block, exec_output)
return (LoadStoreDeclare.subst(iop),
- EACompConstructor.subst(ea_iop)
- + MemAccConstructor.subst(memacc_iop)
- + LoadStoreConstructor.subst(iop),
+ LoadStoreConstructor.subst(iop),
decode_template.subst(iop),
- eaCompExecuteTemplate.subst(ea_iop)
- + memAccExecTemplate.subst(memacc_iop)
- + fullExecTemplate.subst(iop)
+ fullExecTemplate.subst(iop)
+ initiateAccTemplate.subst(iop)
- + completeAccTemplate.subst(iop)
- + memAccSizeTemplate.subst(memacc_iop))
+ + completeAccTemplate.subst(iop))
}};
output header {{
projects / gem5.git / blobdiff