sim: Move the BaseTLB to src/arch/generic/

[gem5.git] / src / arch / mips / isa.cc

diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 3c8c9a9866a0d965844aed4669d1e260a5596b93..164f10d5d03896312cee045ca5eee7dbba307cb2 100644 (file)
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -29,12 +29,14 @@
  */
 
 #include "arch/mips/isa.hh"
-#include "arch/mips/mt_constants.hh"
 #include "arch/mips/mt.hh"
+#include "arch/mips/mt_constants.hh"
 #include "arch/mips/pra_constants.hh"
 #include "base/bitfield.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
+#include "debug/MipsPRA.hh"
+#include "params/MipsISA.hh"
 
 namespace MipsISA
 {
@@ -86,19 +88,8 @@ ISA::miscRegNames[NumMiscRegs] =
     "LLFlag"
 };
 
-ISA::ISA()
-{
-    init();
-}
-
-ISA::ISA(BaseCPU *_cpu)
-{
-    cpu = _cpu;
-    init();
-}
-
-void
-ISA::init()
+ISA::ISA(Params *p)
+    : SimObject(p), numThreads(p->num_threads), numVpes(p->num_vpes)
 {
     miscRegFile.resize(NumMiscRegs);
     bankType.resize(NumMiscRegs);
@@ -113,21 +104,7 @@ ISA::init()
     for (int i = 0; i < NumMiscRegs; i++) {
         miscRegFile_WriteMask[i].push_back(0);
     }
-    clear(0);
-}
-
-void
-ISA::clear(unsigned tid_or_vpn)
-{
-    for(int i = 0; i < NumMiscRegs; i++) {
-        miscRegFile[i][tid_or_vpn] = 0;
-        miscRegFile_WriteMask[i][tid_or_vpn] = (long unsigned int)(-1);
-    }
-}
 
-void
-ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
-{
     // Initialize all Per-VPE regs
     uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL,
                                 MISCREG_VPE_CONF0, MISCREG_VPE_CONF1,
@@ -140,8 +117,8 @@ ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
                               };
     uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
     for (int i = 0; i < num_vpe_regs; i++) {
-        if (num_vpes > 1) {
-            miscRegFile[per_vpe_regs[i]].resize(num_vpes);
+        if (numVpes > 1) {
+            miscRegFile[per_vpe_regs[i]].resize(numVpes);
         }
         bankType[per_vpe_regs[i]] = perVirtProcessor;
     }
@@ -157,29 +134,40 @@ ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
     uint32_t num_tc_regs = sizeof(per_tc_regs) /  4;
 
     for (int i = 0; i < num_tc_regs; i++) {
-        miscRegFile[per_tc_regs[i]].resize(num_threads);
+        miscRegFile[per_tc_regs[i]].resize(numThreads);
         bankType[per_tc_regs[i]] = perThreadContext;
     }
 
+    clear();
+}
 
-    if (num_vpes > 1) {
-        for (int i=1; i < num_vpes; i++) {
-            clear(i);
-        }
-    }
+const MipsISAParams *
+ISA::params() const
+{
+    return dynamic_cast<const Params *>(_params);
+}
+
+void
+ISA::clear()
+{
+    for(int i = 0; i < NumMiscRegs; i++) {
+        for (int j = 0; j < miscRegFile[i].size(); j++)
+            miscRegFile[i][j] = 0;
 
+        for (int k = 0; k < miscRegFile_WriteMask[i].size(); k++)
+            miscRegFile_WriteMask[i][k] = (long unsigned int)(-1);
+    }
 }
 
-//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
+
 void
-ISA::reset(std::string core_name, ThreadID num_threads,
-                   unsigned num_vpes, BaseCPU *_cpu)
+ISA::configCP()
 {
     DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
-            num_threads, num_vpes);
-    cpu = _cpu;
+            numThreads, numVpes);
 
-    MipsISA::CoreSpecific &cp = cpu->coreParams;
+    CoreSpecific cp;
+    panic("CP state must be set before the following code is used");
 
     // Do Default CP0 initialization HERE
 
@@ -357,8 +345,8 @@ ISA::reset(std::string core_name, ThreadID num_threads,
     // MVPConf0
     MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
     mvpConf0.tca = 1;
-    mvpConf0.pvpe = num_vpes - 1;
-    mvpConf0.ptc = num_threads - 1;
+    mvpConf0.pvpe = numVpes - 1;
+    mvpConf0.ptc = numThreads - 1;
     setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0);
 
     // VPEConf0
@@ -367,7 +355,7 @@ ISA::reset(std::string core_name, ThreadID num_threads,
     setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0);
 
     // TCBind
-    for (ThreadID tid = 0; tid < num_threads; tid++) {
+    for (ThreadID tid = 0; tid < numThreads; tid++) {
         TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid);
         tcBind.curTC = tid;
         setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
@@ -384,7 +372,7 @@ ISA::reset(std::string core_name, ThreadID num_threads,
     setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
 
     // Set Dynamically Allocatable bit to 1 for all other threads
-    for (ThreadID tid = 1; tid < num_threads; tid++) {
+    for (ThreadID tid = 1; tid < numThreads; tid++) {
         tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
         tcStatus.da = 1;
         setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
@@ -499,7 +487,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val,
 
     miscRegFile[misc_reg][reg_sel] = cp0_val;
 
-    scheduleCP0Update(1);
+    scheduleCP0Update(tc->getCpuPtr(), Cycles(1));
 }
 
 /**
@@ -528,19 +516,19 @@ ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
 }
 
 void
-ISA::scheduleCP0Update(int delay)
+ISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay)
 {
     if (!cp0Updated) {
         cp0Updated = true;
 
         //schedule UPDATE
         CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
-        cpu->schedule(cp0_event, curTick + cpu->ticks(delay));
+        cpu->schedule(cp0_event, cpu->clockEdge(delay));
     }
 }
 
 void
-ISA::updateCPU()
+ISA::updateCPU(BaseCPU *cpu)
 {
     ///////////////////////////////////////////////////////////////////
     //
@@ -578,7 +566,7 @@ ISA::CP0Event::process()
     switch (cp0EventType)
     {
       case UpdateCP0:
-        cp0->updateCPU();
+        cp0->updateCPU(cpu);
         break;
     }
 }
@@ -590,9 +578,9 @@ ISA::CP0Event::description() const
 }
 
 void
-ISA::CP0Event::scheduleEvent(int delay)
+ISA::CP0Event::scheduleEvent(Cycles delay)
 {
-    cpu->reschedule(this, curTick + cpu->ticks(delay), true);
+    cpu->reschedule(this, cpu->clockEdge(delay), true);
 }
 
 void
@@ -603,3 +591,9 @@ ISA::CP0Event::unscheduleEvent()
 }
 
 }
+
+MipsISA::ISA *
+MipsISAParams::create()
+{
+    return new MipsISA::ISA(this);
+}