*/
#include "arch/mips/isa.hh"
-#include "arch/mips/mt_constants.hh"
#include "arch/mips/mt.hh"
+#include "arch/mips/mt_constants.hh"
#include "arch/mips/pra_constants.hh"
#include "base/bitfield.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/MipsPRA.hh"
+#include "params/MipsISA.hh"
namespace MipsISA
{
"LLFlag"
};
-ISA::ISA(uint8_t num_threads, uint8_t num_vpes)
+ISA::ISA(Params *p)
+ : SimObject(p), numThreads(p->num_threads), numVpes(p->num_vpes)
{
- numThreads = num_threads;
- numVpes = num_vpes;
-
miscRegFile.resize(NumMiscRegs);
bankType.resize(NumMiscRegs);
clear();
}
+const MipsISAParams *
+ISA::params() const
+{
+ return dynamic_cast<const Params *>(_params);
+}
+
void
ISA::clear()
{
miscRegFile[misc_reg][reg_sel] = cp0_val;
- scheduleCP0Update(tc->getCpuPtr(), 1);
+ scheduleCP0Update(tc->getCpuPtr(), Cycles(1));
}
/**
}
void
-ISA::scheduleCP0Update(BaseCPU *cpu, int delay)
+ISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay)
{
if (!cp0Updated) {
cp0Updated = true;
//schedule UPDATE
CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
- cpu->schedule(cp0_event, curTick() + cpu->ticks(delay));
+ cpu->schedule(cp0_event, cpu->clockEdge(delay));
}
}
}
void
-ISA::CP0Event::scheduleEvent(int delay)
+ISA::CP0Event::scheduleEvent(Cycles delay)
{
- cpu->reschedule(this, curTick() + cpu->ticks(delay), true);
+ cpu->reschedule(this, cpu->clockEdge(delay), true);
}
void
}
}
+
+MipsISA::ISA *
+MipsISAParams::create()
+{
+ return new MipsISA::ISA(this);
+}