sim: Move the BaseTLB to src/arch/generic/

[gem5.git] / src / arch / mips / isa.cc

diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 6a525ed3a877893f040e14c91a89e451cb7c64a6..164f10d5d03896312cee045ca5eee7dbba307cb2 100644 (file)
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -36,6 +36,7 @@
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "debug/MipsPRA.hh"
+#include "params/MipsISA.hh"
 
 namespace MipsISA
 {
@@ -87,11 +88,9 @@ ISA::miscRegNames[NumMiscRegs] =
     "LLFlag"
 };
 
-ISA::ISA(uint8_t num_threads, uint8_t num_vpes)
+ISA::ISA(Params *p)
+    : SimObject(p), numThreads(p->num_threads), numVpes(p->num_vpes)
 {
-    numThreads = num_threads;
-    numVpes = num_vpes;
-
     miscRegFile.resize(NumMiscRegs);
     bankType.resize(NumMiscRegs);
 
@@ -142,6 +141,12 @@ ISA::ISA(uint8_t num_threads, uint8_t num_vpes)
     clear();
 }
 
+const MipsISAParams *
+ISA::params() const
+{
+    return dynamic_cast<const Params *>(_params);
+}
+
 void
 ISA::clear()
 {
@@ -482,7 +487,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val,
 
     miscRegFile[misc_reg][reg_sel] = cp0_val;
 
-    scheduleCP0Update(tc->getCpuPtr(), 1);
+    scheduleCP0Update(tc->getCpuPtr(), Cycles(1));
 }
 
 /**
@@ -511,14 +516,14 @@ ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
 }
 
 void
-ISA::scheduleCP0Update(BaseCPU *cpu, int delay)
+ISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay)
 {
     if (!cp0Updated) {
         cp0Updated = true;
 
         //schedule UPDATE
         CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
-        cpu->schedule(cp0_event, curTick() + cpu->ticks(delay));
+        cpu->schedule(cp0_event, cpu->clockEdge(delay));
     }
 }
 
@@ -573,9 +578,9 @@ ISA::CP0Event::description() const
 }
 
 void
-ISA::CP0Event::scheduleEvent(int delay)
+ISA::CP0Event::scheduleEvent(Cycles delay)
 {
-    cpu->reschedule(this, curTick() + cpu->ticks(delay), true);
+    cpu->reschedule(this, cpu->clockEdge(delay), true);
 }
 
 void
@@ -586,3 +591,9 @@ ISA::CP0Event::unscheduleEvent()
 }
 
 }
+
+MipsISA::ISA *
+MipsISAParams::create()
+{
+    return new MipsISA::ISA(this);
+}