arch,cpu: Add a setThreadContext method to the ISA class.

[gem5.git] / src / arch / mips / isa.hh

diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 73cb0462ac366445e0d77025e0847bde67f076ad..301f573df58af4a604a02db61c5b7918c6e7e962 100644 (file)
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -72,9 +72,6 @@ namespace MipsISA
         std::vector<BankType> bankType;
 
       public:
-        void clear(ThreadContext *tc) { clear(); }
-
-      protected:
         void clear();
 
       public:
@@ -94,15 +91,14 @@ namespace MipsISA
         RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
 
         //template <class TC>
-        RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
+        RegVal readMiscReg(int misc_reg, ThreadID tid = 0);
 
         RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val);
         void setRegMask(int misc_reg, RegVal val, ThreadID tid = 0);
         void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0);
 
         //template <class TC>
-        void setMiscReg(int misc_reg, RegVal val,
-                        ThreadContext *tc, ThreadID tid=0);
+        void setMiscReg(int misc_reg, RegVal val, ThreadID tid=0);
 
         //////////////////////////////////////////////////////////
         //
@@ -132,60 +128,20 @@ namespace MipsISA
         static std::string miscRegNames[NumMiscRegs];
 
       public:
-        void startup(ThreadContext *tc) {}
-
-        /// Explicitly import the otherwise hidden startup
-        using BaseISA::startup;
-
         const Params *params() const;
 
         ISA(Params *p);
 
         RegId flattenRegId(const RegId& regId) const { return regId; }
 
-        int
-        flattenIntIndex(int reg) const
-        {
-            return reg;
-        }
-
-        int
-        flattenFloatIndex(int reg) const
-        {
-            return reg;
-        }
-
-        int
-        flattenVecIndex(int reg) const
-        {
-            return reg;
-        }
-
-        int
-        flattenVecElemIndex(int reg) const
-        {
-            return reg;
-        }
-
-        int
-        flattenVecPredIndex(int reg) const
-        {
-            return reg;
-        }
-
+        int flattenIntIndex(int reg) const { return reg; }
+        int flattenFloatIndex(int reg) const { return reg; }
+        int flattenVecIndex(int reg) const { return reg; }
+        int flattenVecElemIndex(int reg) const { return reg; }
+        int flattenVecPredIndex(int reg) const { return reg; }
         // dummy
-        int
-        flattenCCIndex(int reg) const
-        {
-            return reg;
-        }
-
-        int
-        flattenMiscIndex(int reg) const
-        {
-            return reg;
-        }
-
+        int flattenCCIndex(int reg) const { return reg; }
+        int flattenMiscIndex(int reg) const { return reg; }
     };
 }