cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.

[gem5.git] / src / arch / mips / isa.hh

diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 15c043dc06b45d872c721fc6b18dd7c87f9535de..c601cfc1eda74c442e963780acb5594316af777c 100644 (file)
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -31,29 +31,37 @@
 #ifndef __ARCH_MIPS_ISA_HH__
 #define __ARCH_MIPS_ISA_HH__
 
-#include <string>
 #include <queue>
+#include <string>
 #include <vector>
 
 #include "arch/mips/registers.hh"
 #include "arch/mips/types.hh"
 #include "sim/eventq.hh"
-#include "sim/faults.hh"
+#include "sim/fault_fwd.hh"
+#include "sim/sim_object.hh"
 
 class BaseCPU;
 class Checkpoint;
 class EventManager;
+struct MipsISAParams;
 class ThreadContext;
 
 namespace MipsISA
 {
-    class ISA
+    class ISA : public SimObject
     {
       public:
         // The MIPS name for this file is CP0 or Coprocessor 0
         typedef ISA CP0;
 
+        typedef MipsISAParams Params;
+
       protected:
+        // Number of threads and vpes an individual ISA state can handle
+        uint8_t numThreads;
+        uint8_t numVpes;
+
         enum BankType {
             perProcessor,
             perThreadContext,
@@ -64,20 +72,10 @@ namespace MipsISA
         std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
         std::vector<BankType> bankType;
 
-        BaseCPU *cpu;
-
       public:
-        ISA();
-        ISA(BaseCPU *_cpu);
-
-        void init();
-
-        void clear(unsigned tid_or_vpn = 0);
-
-        void reset(std::string core_name, ThreadID num_threads,
-                   unsigned num_vpes, BaseCPU *_cpu);
+        void clear();
 
-        void expandForMultithreading(ThreadID num_threads, unsigned num_vpes);
+        void configCP();
 
         unsigned getVPENum(ThreadID tid);
 
@@ -140,18 +138,18 @@ namespace MipsISA
             const char *description() const;
 
             /** Schedule This Event */
-            void scheduleEvent(int delay);
+            void scheduleEvent(Cycles delay);
 
             /** Unschedule This Event */
             void unscheduleEvent();
         };
 
         // Schedule a CP0 Update Event
-        void scheduleCP0Update(int delay = 0);
+        void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
 
         // If any changes have been made, then check the state for changes
         // and if necessary alert the CPU
-        void updateCPU();
+        void updateCPU(BaseCPU *cpu);
 
         // Keep a List of CPU Events that need to be deallocated
         std::queue<CP0Event*> cp0EventRemoveList;
@@ -159,6 +157,14 @@ namespace MipsISA
         static std::string miscRegNames[NumMiscRegs];
 
       public:
+        void startup(ThreadContext *tc) {}
+
+        /// Explicitly import the otherwise hidden startup
+        using SimObject::startup;
+
+        const Params *params() const;
+
+        ISA(Params *p);
 
         int
         flattenIntIndex(int reg)
@@ -172,8 +178,12 @@ namespace MipsISA
             return reg;
         }
 
-        void serialize(std::ostream &os);
-        void unserialize(Checkpoint *cp, const std::string &section);
+        // dummy
+        int
+        flattenCCIndex(int reg)
+        {
+            return reg;
+        }
     };
 }