#ifndef __ARCH_MIPS_ISA_HH__
#define __ARCH_MIPS_ISA_HH__
-#include <string>
#include <queue>
+#include <string>
#include <vector>
#include "arch/mips/registers.hh"
#include "arch/mips/types.hh"
#include "sim/eventq.hh"
-#include "sim/faults.hh"
+#include "sim/fault_fwd.hh"
+#include "sim/sim_object.hh"
class BaseCPU;
class Checkpoint;
class EventManager;
+struct MipsISAParams;
class ThreadContext;
namespace MipsISA
{
- class ISA
+ class ISA : public SimObject
{
public:
// The MIPS name for this file is CP0 or Coprocessor 0
typedef ISA CP0;
+ typedef MipsISAParams Params;
+
protected:
+ // Number of threads and vpes an individual ISA state can handle
+ uint8_t numThreads;
+ uint8_t numVpes;
+
enum BankType {
perProcessor,
perThreadContext,
std::vector<BankType> bankType;
public:
- ISA();
-
- void init();
-
- void clear(unsigned tid_or_vpn = 0);
-
- void reset(std::string core_name, ThreadID num_threads,
- unsigned num_vpes, BaseCPU *cpu);
+ void clear();
- void expandForMultithreading(ThreadID num_threads, unsigned num_vpes);
+ void configCP();
unsigned getVPENum(ThreadID tid);
const char *description() const;
/** Schedule This Event */
- void scheduleEvent(int delay);
+ void scheduleEvent(Cycles delay);
/** Unschedule This Event */
void unscheduleEvent();
};
// Schedule a CP0 Update Event
- void scheduleCP0Update(BaseCPU *cpu, int delay = 0);
+ void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
// If any changes have been made, then check the state for changes
// and if necessary alert the CPU
static std::string miscRegNames[NumMiscRegs];
public:
+ void startup(ThreadContext *tc) {}
+
+ /// Explicitly import the otherwise hidden startup
+ using SimObject::startup;
+
+ const Params *params() const;
+
+ ISA(Params *p);
int
flattenIntIndex(int reg)
return reg;
}
- void serialize(EventManager *em, std::ostream &os)
- {}
- void unserialize(EventManager *em, Checkpoint *cp,
- const std::string §ion)
- {}
+ // dummy
+ int
+ flattenCCIndex(int reg)
+ {
+ return reg;
+ }
};
}