#include "arch/mips/types.hh"
#include "sim/eventq.hh"
#include "sim/fault_fwd.hh"
+#include "sim/sim_object.hh"
class BaseCPU;
class Checkpoint;
class EventManager;
+struct MipsISAParams;
class ThreadContext;
namespace MipsISA
{
- class ISA
+ class ISA : public SimObject
{
public:
// The MIPS name for this file is CP0 or Coprocessor 0
typedef ISA CP0;
+ typedef MipsISAParams Params;
+
protected:
// Number of threads and vpes an individual ISA state can handle
uint8_t numThreads;
std::vector<BankType> bankType;
public:
- ISA(uint8_t num_threads = 1, uint8_t num_vpes = 1);
-
void clear();
void configCP();
static std::string miscRegNames[NumMiscRegs];
public:
+ void startup(ThreadContext *tc) {}
+
+ /// Explicitly import the otherwise hidden startup
+ using SimObject::startup;
+
+ const Params *params() const;
+
+ ISA(Params *p);
int
flattenIntIndex(int reg)
return reg;
}
- void serialize(EventManager *em, std::ostream &os)
- {}
- void unserialize(EventManager *em, Checkpoint *cp,
- const std::string §ion)
- {}
+ // dummy
+ int
+ flattenCCIndex(int reg)
+ {
+ return reg;
+ }
};
}