#ifndef __ARCH_MIPS_ISA_HH__
#define __ARCH_MIPS_ISA_HH__
-#include "arch/mips/misc_regfile.hh"
+#include <queue>
+#include <string>
+#include <vector>
+
+#include "arch/mips/registers.hh"
#include "arch/mips/types.hh"
+#include "sim/eventq.hh"
+#include "sim/sim_object.hh"
+class BaseCPU;
class Checkpoint;
class EventManager;
+struct MipsISAParams;
+class ThreadContext;
namespace MipsISA
{
- class ISA
+ class ISA : public SimObject
{
+ public:
+ // The MIPS name for this file is CP0 or Coprocessor 0
+ typedef ISA CP0;
+
+ typedef MipsISAParams Params;
+
protected:
- MiscRegFile miscRegFile;
+ // Number of threads and vpes an individual ISA state can handle
+ uint8_t numThreads;
+ uint8_t numVpes;
+
+ enum BankType {
+ perProcessor,
+ perThreadContext,
+ perVirtProcessor
+ };
+
+ std::vector<std::vector<MiscReg> > miscRegFile;
+ std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
+ std::vector<BankType> bankType;
public:
+ void clear();
- void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
+ void configCP();
+
+ unsigned getVPENum(ThreadID tid) const;
+
+ //////////////////////////////////////////////////////////
+ //
+ // READ/WRITE CP0 STATE
+ //
+ //
+ //////////////////////////////////////////////////////////
+ //@TODO: MIPS MT's register view automatically connects
+ // Status to TCStatus depending on current thread
+ void updateCP0ReadView(int misc_reg, ThreadID tid) { }
+ MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
+
+ //template <class TC>
+ MiscReg readMiscReg(int misc_reg,
+ ThreadContext *tc, ThreadID tid = 0);
+
+ MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
+ void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid = 0);
+ void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
+ ThreadID tid = 0);
+
+ //template <class TC>
+ void setMiscReg(int misc_reg, const MiscReg &val,
+ ThreadContext *tc, ThreadID tid = 0);
+
+ //////////////////////////////////////////////////////////
+ //
+ // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
+ // TO SCHEDULE EVENTS
+ //
+ //////////////////////////////////////////////////////////
+
+ // Flag that is set when CP0 state has been written to.
+ bool cp0Updated;
+
+ // Enumerated List of CP0 Event Types
+ enum CP0EventType {
+ UpdateCP0
+ };
+
+ // Declare A CP0Event Class for scheduling
+ class CP0Event : public Event
{
- miscRegFile.expandForMultithreading(num_threads, num_vpes);
- }
+ protected:
+ ISA::CP0 *cp0;
+ BaseCPU *cpu;
+ CP0EventType cp0EventType;
+ Fault fault;
- void reset(std::string core_name, ThreadID num_threads,
- unsigned num_vpes, BaseCPU *_cpu)
- {
- miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
- }
+ public:
+ /** Constructs a CP0 event. */
+ CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type);
- int instAsid()
- {
- return miscRegFile.getInstAsid();
- }
+ /** Process this event. */
+ virtual void process();
- int dataAsid()
- {
- return miscRegFile.getDataAsid();
- }
+ /** Returns the description of this event. */
+ const char *description() const;
- void clear();
+ /** Schedule This Event */
+ void scheduleEvent(Cycles delay);
- MiscReg readMiscRegNoEffect(int miscReg);
- MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+ /** Unschedule This Event */
+ void unscheduleEvent();
+ };
- void setMiscRegNoEffect(int miscReg, const MiscReg val);
- void setMiscReg(int miscReg, const MiscReg val,
- ThreadContext *tc);
+ // Schedule a CP0 Update Event
+ void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
+
+ // If any changes have been made, then check the state for changes
+ // and if necessary alert the CPU
+ void updateCPU(BaseCPU *cpu);
+
+ // Keep a List of CPU Events that need to be deallocated
+ std::queue<CP0Event*> cp0EventRemoveList;
+
+ static std::string miscRegNames[NumMiscRegs];
+
+ public:
+ void startup(ThreadContext *tc) {}
+
+ /// Explicitly import the otherwise hidden startup
+ using SimObject::startup;
+
+ const Params *params() const;
+
+ ISA(Params *p);
int
- flattenIntIndex(int reg)
+ flattenIntIndex(int reg) const
{
return reg;
}
int
- flattenFloatIndex(int reg)
+ flattenFloatIndex(int reg) const
{
return reg;
}
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string §ion);
+ // dummy
+ int
+ flattenCCIndex(int reg) const
+ {
+ return reg;
+ }
- ISA()
+ int
+ flattenMiscIndex(int reg) const
{
- clear();
+ return reg;
}
+
};
}