/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Authors: Gabe Black
* Korey Sewell
+ * Jaidev Patwardhan
*/
#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
#define __ARCH_MIPS_ISA_TRAITS_HH__
-#include "arch/mips/constants.hh"
#include "arch/mips/types.hh"
-#include "arch/mips/regfile/regfile.hh"
-#include "arch/mips/faults.hh"
-#include "arch/mips/utility.hh"
-#include "base/misc.hh"
-#include "config/full_system.hh"
-#include "sim/byteswap.hh"
-#include "sim/host.hh"
-#include "sim/faults.hh"
-
-#include <vector>
-
-class FastCPU;
-class FullCPU;
-class Checkpoint;
-class ThreadContext;
-
-namespace LittleEndianGuest {};
-
-#define TARGET_MIPS
-
-class StaticInst;
-class StaticInstPtr;
-
-class SyscallReturn {
- public:
- template <class T>
- SyscallReturn(T v, bool s)
- {
- retval = (uint32_t)v;
- success = s;
- }
-
- template <class T>
- SyscallReturn(T v)
- {
- success = (v >= 0);
- retval = (uint32_t)v;
- }
-
- ~SyscallReturn() {}
-
- SyscallReturn& operator=(const SyscallReturn& s) {
- retval = s.retval;
- success = s.success;
- return *this;
- }
-
- bool successful() { return success; }
- uint64_t value() { return retval; }
-
-
- private:
- uint64_t retval;
- bool success;
-};
+#include "base/types.hh"
+#include "cpu/static_inst_fwd.hh"
+
+namespace LittleEndianGuest {}
namespace MipsISA
{
- using namespace LittleEndianGuest;
-
- static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
- {
- if (return_value.successful()) {
- // no error
- regs->setIntReg(SyscallSuccessReg, 0);
- regs->setIntReg(ReturnValueReg1, return_value.value());
- } else {
- // got an error, return details
- regs->setIntReg(SyscallSuccessReg, (IntReg) -1);
- regs->setIntReg(ReturnValueReg1, -return_value.value());
- }
- }
-
- StaticInstPtr decodeInst(ExtMachInst);
-
- static inline ExtMachInst
- makeExtMI(MachInst inst, const uint64_t &pc) {
-#if FULL_SYSTEM
- ExtMachInst ext_inst = inst;
- if (pc && 0x1)
- return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
- else
- return ext_inst;
-#else
- return ExtMachInst(inst);
-#endif
- }
-
- /**
- * Function to insure ISA semantics about 0 registers.
- * @param tc The thread context.
- */
- template <class TC>
- void zeroRegisters(TC *tc);
-
-// const Addr MaxAddr = (Addr)-1;
-
- void copyRegs(ThreadContext *src, ThreadContext *dest);
-
- // Machine operations
-
- void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
- int regnum);
-
- void restoreMachineReg(RegFile ®s, const AnyReg ®,
- int regnum);
-
-#if 0
- static void serializeSpecialRegs(const Serializable::Proxy &proxy,
- const RegFile ®s);
-
- static void unserializeSpecialRegs(const IniFile *db,
- const std::string &category,
- ConfigNode *node,
- RegFile ®s);
-#endif
-
- static inline Addr alignAddress(const Addr &addr,
- unsigned int nbytes) {
- return (addr & ~(nbytes - 1));
- }
-
- // Instruction address compression hooks
- static inline Addr realPCToFetchPC(const Addr &addr) {
- return addr;
- }
-
- static inline Addr fetchPCToRealPC(const Addr &addr) {
- return addr;
- }
-
- // the size of "fetched" instructions (not necessarily the size
- // of real instructions for PISA)
- static inline size_t fetchInstSize() {
- return sizeof(MachInst);
- }
-
- static inline MachInst makeRegisterCopy(int dest, int src) {
- panic("makeRegisterCopy not implemented");
- return 0;
- }
+using namespace LittleEndianGuest;
+
+StaticInstPtr decodeInst(ExtMachInst);
+
+// MIPS DOES have a delay slot
+#define ISA_HAS_DELAY_SLOT 1
+
+const Addr PageShift = 13;
+const Addr PageBytes = ULL(1) << PageShift;
+const Addr Page_Mask = ~(PageBytes - 1);
+const Addr PageOffset = PageBytes - 1;
+
+
+////////////////////////////////////////////////////////////////////////
+//
+// Translation stuff
+//
+
+const Addr PteShift = 3;
+const Addr NPtePageShift = PageShift - PteShift;
+const Addr NPtePage = ULL(1) << NPtePageShift;
+const Addr PteMask = NPtePage - 1;
+
+//// All 'Mapped' segments go through the TLB
+//// All other segments are translated by dropping the MSB, to give
+//// the corresponding physical address
+// User Segment - Mapped
+const Addr USegBase = ULL(0x0);
+const Addr USegEnd = ULL(0x7FFFFFFF);
+
+// Kernel Segment 0 - Unmapped
+const Addr KSeg0End = ULL(0x9FFFFFFF);
+const Addr KSeg0Base = ULL(0x80000000);
+const Addr KSeg0Mask = ULL(0x1FFFFFFF);
+
+// Kernel Segment 1 - Unmapped, Uncached
+const Addr KSeg1End = ULL(0xBFFFFFFF);
+const Addr KSeg1Base = ULL(0xA0000000);
+const Addr KSeg1Mask = ULL(0x1FFFFFFF);
+
+// Kernel/Supervisor Segment - Mapped
+const Addr KSSegEnd = ULL(0xDFFFFFFF);
+const Addr KSSegBase = ULL(0xC0000000);
+
+// Kernel Segment 3 - Mapped
+const Addr KSeg3End = ULL(0xFFFFFFFF);
+const Addr KSeg3Base = ULL(0xE0000000);
+
+
+inline Addr Phys2K0Seg(Addr addr)
+{
+ return addr | KSeg0Base;
+}
+
+
+const unsigned VABits = 32;
+const unsigned PABits = 32; // Is this correct?
+const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
+const Addr VAddrUnImplMask = ~VAddrImplMask;
+inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
+inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
+inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
+
+const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
+
+////////////////////////////////////////////////////////////////////////
+//
+// Interrupt levels
+//
+enum InterruptLevels
+{
+ INTLEVEL_SOFTWARE_MIN = 4,
+ INTLEVEL_SOFTWARE_MAX = 19,
+
+ INTLEVEL_EXTERNAL_MIN = 20,
+ INTLEVEL_EXTERNAL_MAX = 34,
+
+ INTLEVEL_IRQ0 = 20,
+ INTLEVEL_IRQ1 = 21,
+ INTINDEX_ETHERNET = 0,
+ INTINDEX_SCSI = 1,
+ INTLEVEL_IRQ2 = 22,
+ INTLEVEL_IRQ3 = 23,
+
+ INTLEVEL_SERIAL = 33,
+
+ NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
};
-using namespace MipsISA;
+// MIPS modes
+enum mode_type
+{
+ mode_kernel = 0, // kernel
+ mode_supervisor = 1, // supervisor
+ mode_user = 2, // user mode
+ mode_debug = 3, // debug mode
+ mode_number // number of modes
+};
+
+// return a no-op instruction... used for instruction fetch faults
+const ExtMachInst NoopMachInst = 0x00000000;
+
+const int LogVMPageSize = 13; // 8K bytes
+const int VMPageSize = (1 << LogVMPageSize);
+
+const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
+
+const int MachineBytes = 4;
+const int WordBytes = 4;
+const int HalfwordBytes = 2;
+const int ByteBytes = 1;
+
+const int ANNOTE_NONE = 0;
+const uint32_t ITOUCH_ANNOTE = 0xffffffff;
+
+const bool HasUnalignedMemAcc = true;
+
+} // namespace MipsISA
#endif // __ARCH_MIPS_ISA_TRAITS_HH__
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