#define __ARCH_MIPS_ISA_TRAITS_HH__
#include "arch/mips/types.hh"
-#include "arch/mips/mips_core_specific.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
+#include "cpu/static_inst_fwd.hh"
-namespace LittleEndianGuest {};
-
-class StaticInstPtr;
+namespace LittleEndianGuest {}
namespace MipsISA
{
const Addr KSeg3Base = ULL(0xE0000000);
-// For loading... XXX This maybe could be USegEnd?? --ali
-const Addr LoadAddrMask = ULL(0xffffffffff);
-
inline Addr Phys2K0Seg(Addr addr)
{
return addr | KSeg0Base;
const int ANNOTE_NONE = 0;
const uint32_t ITOUCH_ANNOTE = 0xffffffff;
-};
+const bool HasUnalignedMemAcc = true;
+
+} // namespace MipsISA
#endif // __ARCH_MIPS_ISA_TRAITS_HH__