/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Authors: Gabe Black
* Korey Sewell
+ * Jaidev Patwardhan
*/
#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
#define __ARCH_MIPS_ISA_TRAITS_HH__
#include "arch/mips/types.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
+#include "cpu/static_inst_fwd.hh"
-namespace LittleEndianGuest {};
+namespace LittleEndianGuest {}
-#define TARGET_MIPS
+namespace MipsISA
+{
-class StaticInstPtr;
+using namespace LittleEndianGuest;
-namespace MipsISA
+StaticInstPtr decodeInst(ExtMachInst);
+
+// MIPS DOES have a delay slot
+#define ISA_HAS_DELAY_SLOT 1
+
+const Addr PageShift = 13;
+const Addr PageBytes = ULL(1) << PageShift;
+const Addr Page_Mask = ~(PageBytes - 1);
+const Addr PageOffset = PageBytes - 1;
+
+
+////////////////////////////////////////////////////////////////////////
+//
+// Translation stuff
+//
+
+const Addr PteShift = 3;
+const Addr NPtePageShift = PageShift - PteShift;
+const Addr NPtePage = ULL(1) << NPtePageShift;
+const Addr PteMask = NPtePage - 1;
+
+//// All 'Mapped' segments go through the TLB
+//// All other segments are translated by dropping the MSB, to give
+//// the corresponding physical address
+// User Segment - Mapped
+const Addr USegBase = ULL(0x0);
+const Addr USegEnd = ULL(0x7FFFFFFF);
+
+// Kernel Segment 0 - Unmapped
+const Addr KSeg0End = ULL(0x9FFFFFFF);
+const Addr KSeg0Base = ULL(0x80000000);
+const Addr KSeg0Mask = ULL(0x1FFFFFFF);
+
+// Kernel Segment 1 - Unmapped, Uncached
+const Addr KSeg1End = ULL(0xBFFFFFFF);
+const Addr KSeg1Base = ULL(0xA0000000);
+const Addr KSeg1Mask = ULL(0x1FFFFFFF);
+
+// Kernel/Supervisor Segment - Mapped
+const Addr KSSegEnd = ULL(0xDFFFFFFF);
+const Addr KSSegBase = ULL(0xC0000000);
+
+// Kernel Segment 3 - Mapped
+const Addr KSeg3End = ULL(0xFFFFFFFF);
+const Addr KSeg3Base = ULL(0xE0000000);
+
+
+inline Addr Phys2K0Seg(Addr addr)
+{
+ return addr | KSeg0Base;
+}
+
+
+const unsigned VABits = 32;
+const unsigned PABits = 32; // Is this correct?
+const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
+const Addr VAddrUnImplMask = ~VAddrImplMask;
+inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
+inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
+inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
+
+const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
+
+////////////////////////////////////////////////////////////////////////
+//
+// Interrupt levels
+//
+enum InterruptLevels
{
- using namespace LittleEndianGuest;
-
- StaticInstPtr decodeInst(ExtMachInst);
-
- // MIPS DOES a delay slot
- #define ISA_HAS_DELAY_SLOT 1
-
- const Addr PageShift = 13;
- const Addr PageBytes = ULL(1) << PageShift;
- const Addr PageMask = ~(PageBytes - 1);
- const Addr PageOffset = PageBytes - 1;
-
- // return a no-op instruction... used for instruction fetch faults
- const ExtMachInst NoopMachInst = 0x00000000;
-
- // Constants Related to the number of registers
- const int NumIntArchRegs = 32;
- const int NumIntSpecialRegs = 2;
- const int NumFloatArchRegs = 32;
- const int NumFloatSpecialRegs = 5;
- const int NumControlRegs = 265;
- const int NumInternalProcRegs = 0;
-
- const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
- const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
- const int NumMiscRegs = NumControlRegs;
-
- const int TotalNumRegs = NumIntRegs + NumFloatRegs +
- NumMiscRegs + 0/*NumInternalProcRegs*/;
-
- const int TotalDataRegs = NumIntRegs + NumFloatRegs;
-
- // Static instruction parameters
- const int MaxInstSrcRegs = 3;
- const int MaxInstDestRegs = 2;
-
- // semantically meaningful register indices
- const int ZeroReg = 0;
- const int AssemblerReg = 1;
- const int ReturnValueReg = 2;
- const int ReturnValueReg1 = 2;
- const int ReturnValueReg2 = 3;
- const int ArgumentReg0 = 4;
- const int ArgumentReg1 = 5;
- const int ArgumentReg2 = 6;
- const int ArgumentReg3 = 7;
- const int KernelReg0 = 26;
- const int KernelReg1 = 27;
- const int GlobalPointerReg = 28;
- const int StackPointerReg = 29;
- const int FramePointerReg = 30;
- const int ReturnAddressReg = 31;
-
- const int SyscallNumReg = ReturnValueReg1;
- const int SyscallPseudoReturnReg = ReturnValueReg1;
- const int SyscallSuccessReg = ArgumentReg3;
-
- const int LogVMPageSize = 13; // 8K bytes
- const int VMPageSize = (1 << LogVMPageSize);
-
- const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
-
- const int MachineBytes = 4;
- const int WordBytes = 4;
- const int HalfwordBytes = 2;
- const int ByteBytes = 1;
-
- // These help enumerate all the registers for dependence tracking.
- const int FP_Base_DepTag = 34;
- const int Ctrl_Base_DepTag = 257;
-
- const int ANNOTE_NONE = 0;
- const uint32_t ITOUCH_ANNOTE = 0xffffffff;
+ INTLEVEL_SOFTWARE_MIN = 4,
+ INTLEVEL_SOFTWARE_MAX = 19,
+
+ INTLEVEL_EXTERNAL_MIN = 20,
+ INTLEVEL_EXTERNAL_MAX = 34,
+
+ INTLEVEL_IRQ0 = 20,
+ INTLEVEL_IRQ1 = 21,
+ INTINDEX_ETHERNET = 0,
+ INTINDEX_SCSI = 1,
+ INTLEVEL_IRQ2 = 22,
+ INTLEVEL_IRQ3 = 23,
+
+ INTLEVEL_SERIAL = 33,
+
+ NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
+};
+// MIPS modes
+enum mode_type
+{
+ mode_kernel = 0, // kernel
+ mode_supervisor = 1, // supervisor
+ mode_user = 2, // user mode
+ mode_debug = 3, // debug mode
+ mode_number // number of modes
};
-using namespace MipsISA;
+// return a no-op instruction... used for instruction fetch faults
+const ExtMachInst NoopMachInst = 0x00000000;
+
+const int LogVMPageSize = 13; // 8K bytes
+const int VMPageSize = (1 << LogVMPageSize);
+
+const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
+
+const int MachineBytes = 4;
+const int WordBytes = 4;
+const int HalfwordBytes = 2;
+const int ByteBytes = 1;
+
+const int ANNOTE_NONE = 0;
+const uint32_t ITOUCH_ANNOTE = 0xffffffff;
+
+const bool HasUnalignedMemAcc = true;
+
+} // namespace MipsISA
#endif // __ARCH_MIPS_ISA_TRAITS_HH__
projects / gem5.git / blobdiff