/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2006-2007 The Regents of The University of Michigan
* All rights reserved.
*
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
*/
#ifndef __ARCH_MIPS_LOCKED_MEM_HH__
* ISA-specific helper functions for locked memory accesses.
*/
-#include "arch/isa_traits.hh"
-#include "base/misc.hh"
+#include "arch/registers.hh"
+#include "base/logging.hh"
#include "base/trace.hh"
+#include "cpu/base.hh"
+#include "debug/LLSC.hh"
+#include "mem/packet.hh"
#include "mem/request.hh"
-
namespace MipsISA
{
template <class XC>
inline void
-handleLockedRead(XC *xc, Request *req)
+handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
+{
+ if (!xc->readMiscReg(MISCREG_LLFLAG))
+ return;
+
+ Addr locked_addr = xc->readMiscReg(MISCREG_LLADDR) & cacheBlockMask;
+ Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
+
+ if (locked_addr == snoop_addr)
+ xc->setMiscReg(MISCREG_LLFLAG, false);
+}
+
+
+template <class XC>
+inline void
+handleLockedRead(XC *xc, const RequestPtr &req)
{
- xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf);
- xc->setMiscRegNoEffect(LLFlag, true);
- DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n",
- req->getThreadNum(), req->getPaddr() & ~0xf);
+ xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
+ xc->setMiscReg(MISCREG_LLFLAG, true);
+ DPRINTF(LLSC, "[cid:%i]: Load-Link Flag Set & Load-Link"
+ " Address set to %x.\n",
+ req->contextId(), req->getPaddr() & ~0xf);
}
+template <class XC>
+inline void
+handleLockedSnoopHit(XC *xc)
+{
+}
template <class XC>
inline bool
-handleLockedWrite(XC *xc, Request *req)
+handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
{
if (req->isUncacheable()) {
// Funky Turbolaser mailbox access...don't update
req->setExtraData(2);
} else {
// standard store conditional
- bool lock_flag = xc->readMiscRegNoEffect(LLFlag);
- Addr lock_addr = xc->readMiscRegNoEffect(LLAddr);
+ bool lock_flag = xc->readMiscReg(MISCREG_LLFLAG);
+ Addr lock_addr = xc->readMiscReg(MISCREG_LLADDR);
if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
// Lock flag not set or addr mismatch in CPU;
// don't even bother sending to memory system
req->setExtraData(0);
- xc->setMiscRegNoEffect(LLFlag, false);
+ xc->setMiscReg(MISCREG_LLFLAG, false);
// the rest of this code is not architectural;
// it's just a debugging aid to help detect
int stCondFailures = xc->readStCondFailures();
stCondFailures++;
xc->setStCondFailures(stCondFailures);
- if (stCondFailures % 10 == 0) {
- warn("%i: cpu %d: %d consecutive "
+ if (stCondFailures % 100000 == 0) {
+ warn("%i: context %d: %d consecutive "
"store conditional failures\n",
- curTick, xc->cpuId(), stCondFailures);
- }
-
- if (stCondFailures == 5000) {
- panic("Max (5000) Store Conditional Fails Reached. Check Code For Deadlock.\n");
+ curTick(), xc->contextId(), stCondFailures);
}
if (!lock_flag){
- DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n",
- req->getThreadNum());
+ DPRINTF(LLSC, "[cid:%i]: Lock Flag Set, "
+ "Store Conditional Failed.\n",
+ req->contextId());
} else if ((req->getPaddr() & ~0xf) != lock_addr) {
- DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n",
- req->getThreadNum());
+ DPRINTF(LLSC, "[cid:%i]: Load-Link Address Mismatch, "
+ "Store Conditional Failed.\n",
+ req->contextId());
}
// store conditional failed already, so don't issue it to mem
return false;
return true;
}
+template <class XC>
+inline void
+globalClearExclusive(XC *xc)
+{
+ xc->getCpuPtr()->wakeup(xc->threadId());
+}
} // namespace MipsISA