cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.

[gem5.git] / src / arch / mips / locked_mem.hh

diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 021b8cf73aea05bcc23a81c0679debca20219f3b..5b0f8a1b8e5ca76b6edb2a75b3331fcf16668297 100644 (file)
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2006-2007 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -37,28 +49,52 @@
  * ISA-specific helper functions for locked memory accesses.
  */
 
-#include "arch/isa_traits.hh"
+#include "arch/registers.hh"
 #include "base/misc.hh"
 #include "base/trace.hh"
+#include "debug/LLSC.hh"
+#include "mem/packet.hh"
 #include "mem/request.hh"
 
-
 namespace MipsISA
 {
+template <class XC>
+inline void
+handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
+{
+    if (!xc->readMiscReg(MISCREG_LLFLAG))
+        return;
+
+    Addr locked_addr = xc->readMiscReg(MISCREG_LLADDR) & cacheBlockMask;
+    Addr snoop_addr = pkt->getAddr();
+
+    assert((cacheBlockMask & snoop_addr) == snoop_addr);
+
+    if (locked_addr == snoop_addr)
+        xc->setMiscReg(MISCREG_LLFLAG, false);
+}
+
+
 template <class XC>
 inline void
 handleLockedRead(XC *xc, Request *req)
 {
-    xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf);
-    xc->setMiscRegNoEffect(LLFlag, true);
-    DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n",
+    xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
+    xc->setMiscReg(MISCREG_LLFLAG, true);
+    DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link"
+                  " Address set to %x.\n",
             req->threadId(), req->getPaddr() & ~0xf);
 }
 
+template <class XC>
+inline void
+handleLockedSnoopHit(XC *xc)
+{
+}
 
 template <class XC>
 inline bool
-handleLockedWrite(XC *xc, Request *req)
+handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
 {
     if (req->isUncacheable()) {
         // Funky Turbolaser mailbox access...don't update
@@ -66,14 +102,14 @@ handleLockedWrite(XC *xc, Request *req)
         req->setExtraData(2);
     } else {
         // standard store conditional
-        bool lock_flag = xc->readMiscRegNoEffect(LLFlag);
-        Addr lock_addr = xc->readMiscRegNoEffect(LLAddr);
+        bool lock_flag = xc->readMiscReg(MISCREG_LLFLAG);
+        Addr lock_addr = xc->readMiscReg(MISCREG_LLADDR);
 
         if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
             // Lock flag not set or addr mismatch in CPU;
             // don't even bother sending to memory system
             req->setExtraData(0);
-            xc->setMiscRegNoEffect(LLFlag, false);
+            xc->setMiscReg(MISCREG_LLFLAG, false);
 
             // the rest of this code is not architectural;
             // it's just a debugging aid to help detect
@@ -82,21 +118,19 @@ handleLockedWrite(XC *xc, Request *req)
             int stCondFailures = xc->readStCondFailures();
             stCondFailures++;
             xc->setStCondFailures(stCondFailures);
-            if (stCondFailures % 10 == 0) {
+            if (stCondFailures % 100000 == 0) {
                 warn("%i: context %d: %d consecutive "
                      "store conditional failures\n",
-                     curTick, xc->contextId(), stCondFailures);
-            }
-
-            if (stCondFailures == 5000) {
-                panic("Max (5000) Store Conditional Fails Reached. Check Code For Deadlock.\n");
+                     curTick(), xc->contextId(), stCondFailures);
             }
 
             if (!lock_flag){
-                DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n",
+                DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, "
+                              "Store Conditional Failed.\n",
                         req->threadId());
             } else if ((req->getPaddr() & ~0xf) != lock_addr) {
-                DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n",
+                DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, "
+                              "Store Conditional Failed.\n",
                         req->threadId());
             }
             // store conditional failed already, so don't issue it to mem
@@ -107,7 +141,6 @@ handleLockedWrite(XC *xc, Request *req)
     return true;
 }
 
-
 } // namespace MipsISA
 
 #endif