cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.

[gem5.git] / src / arch / mips / locked_mem.hh

diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 1cc08ee3dc2059917558c72103d2110a392253ef..5b0f8a1b8e5ca76b6edb2a75b3331fcf16668297 100644 (file)
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2006-2007 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -40,10 +52,28 @@
 #include "arch/registers.hh"
 #include "base/misc.hh"
 #include "base/trace.hh"
+#include "debug/LLSC.hh"
+#include "mem/packet.hh"
 #include "mem/request.hh"
 
 namespace MipsISA
 {
+template <class XC>
+inline void
+handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
+{
+    if (!xc->readMiscReg(MISCREG_LLFLAG))
+        return;
+
+    Addr locked_addr = xc->readMiscReg(MISCREG_LLADDR) & cacheBlockMask;
+    Addr snoop_addr = pkt->getAddr();
+
+    assert((cacheBlockMask & snoop_addr) == snoop_addr);
+
+    if (locked_addr == snoop_addr)
+        xc->setMiscReg(MISCREG_LLFLAG, false);
+}
+
 
 template <class XC>
 inline void
@@ -56,9 +86,15 @@ handleLockedRead(XC *xc, Request *req)
             req->threadId(), req->getPaddr() & ~0xf);
 }
 
+template <class XC>
+inline void
+handleLockedSnoopHit(XC *xc)
+{
+}
+
 template <class XC>
 inline bool
-handleLockedWrite(XC *xc, Request *req)
+handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
 {
     if (req->isUncacheable()) {
         // Funky Turbolaser mailbox access...don't update