X86: Define a noop ExtMachInst.

[gem5.git] / src / arch / mips / locked_mem.hh

diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 363cf1e90f086b26f0f9f2e6d3f95c04386a2079..8cf94df98adca61fbdd9daa4711bdd721d26a0a0 100644 (file)
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -37,26 +37,75 @@
  * ISA-specific helper functions for locked memory accesses.
  */
 
+#include "arch/registers.hh"
+#include "base/misc.hh"
+#include "base/trace.hh"
 #include "mem/request.hh"
 
 
 namespace MipsISA
 {
+
 template <class XC>
 inline void
 handleLockedRead(XC *xc, Request *req)
 {
+    xc->setMiscRegNoEffect(MISCREG_LLADDR, req->getPaddr() & ~0xf);
+    xc->setMiscRegNoEffect(MISCREG_LLFLAG, true);
+    DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link"
+                  " Address set to %x.\n",
+            req->threadId(), req->getPaddr() & ~0xf);
 }
 
-
 template <class XC>
 inline bool
 handleLockedWrite(XC *xc, Request *req)
 {
+    if (req->isUncacheable()) {
+        // Funky Turbolaser mailbox access...don't update
+        // result register (see stq_c in decoder.isa)
+        req->setExtraData(2);
+    } else {
+        // standard store conditional
+        bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LLFLAG);
+        Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LLADDR);
+
+        if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
+            // Lock flag not set or addr mismatch in CPU;
+            // don't even bother sending to memory system
+            req->setExtraData(0);
+            xc->setMiscRegNoEffect(MISCREG_LLFLAG, false);
+
+            // the rest of this code is not architectural;
+            // it's just a debugging aid to help detect
+            // livelock by warning on long sequences of failed
+            // store conditionals
+            int stCondFailures = xc->readStCondFailures();
+            stCondFailures++;
+            xc->setStCondFailures(stCondFailures);
+            if (stCondFailures % 100000 == 0) {
+                warn("%i: context %d: %d consecutive "
+                     "store conditional failures\n",
+                     curTick, xc->contextId(), stCondFailures);
+            }
+
+            if (!lock_flag){
+                DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, "
+                              "Store Conditional Failed.\n",
+                        req->threadId());
+            } else if ((req->getPaddr() & ~0xf) != lock_addr) {
+                DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, "
+                              "Store Conditional Failed.\n",
+                        req->threadId());
+            }
+            // store conditional failed already, so don't issue it to mem
+            return false;
+        }
+    }
+
     return true;
 }
 
-
 } // namespace MipsISA
 
 #endif