namespace MipsISA
{
+
template <class XC>
inline void
handleLockedRead(XC *xc, Request *req)
{
- xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf);
- xc->setMiscRegNoEffect(LLFlag, true);
- DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n",
+ xc->setMiscRegNoEffect(MISCREG_LLADDR, req->getPaddr() & ~0xf);
+ xc->setMiscRegNoEffect(MISCREG_LLFLAG, true);
+ DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link"
+ " Address set to %x.\n",
req->threadId(), req->getPaddr() & ~0xf);
}
-
template <class XC>
inline bool
handleLockedWrite(XC *xc, Request *req)
req->setExtraData(2);
} else {
// standard store conditional
- bool lock_flag = xc->readMiscRegNoEffect(LLFlag);
- Addr lock_addr = xc->readMiscRegNoEffect(LLAddr);
+ bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LLFLAG);
+ Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LLADDR);
if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
// Lock flag not set or addr mismatch in CPU;
// don't even bother sending to memory system
req->setExtraData(0);
- xc->setMiscRegNoEffect(LLFlag, false);
+ xc->setMiscRegNoEffect(MISCREG_LLFLAG, false);
// the rest of this code is not architectural;
// it's just a debugging aid to help detect
int stCondFailures = xc->readStCondFailures();
stCondFailures++;
xc->setStCondFailures(stCondFailures);
- if (stCondFailures % 10 == 0) {
+ if (stCondFailures % 100000 == 0) {
warn("%i: context %d: %d consecutive "
"store conditional failures\n",
curTick, xc->contextId(), stCondFailures);
}
- if (stCondFailures == 5000) {
- panic("Max (5000) Store Conditional Fails Reached. Check Code For Deadlock.\n");
- }
-
if (!lock_flag){
- DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n",
+ DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, "
+ "Store Conditional Failed.\n",
req->threadId());
} else if ((req->getPaddr() & ~0xf) != lock_addr) {
- DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n",
+ DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, "
+ "Store Conditional Failed.\n",
req->threadId());
}
// store conditional failed already, so don't issue it to mem
return true;
}
-
} // namespace MipsISA
#endif