cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.

[gem5.git] / src / arch / mips / mt.hh

diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index c63c65a7391b63b177d812cc24b674a453ebacb4..64c765f19ec3d3d78133e105f3e21c5307bb4d0c 100755 (executable)
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -37,16 +37,16 @@
  * ISA-specific helper functions for multithreaded execution.
  */
 
+#include <iostream>
+
 #include "arch/mips/faults.hh"
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/mt_constants.hh"
 #include "arch/mips/pra_constants.hh"
 #include "arch/mips/registers.hh"
 #include "base/bitfield.hh"
-#include "base/trace.hh"
 #include "base/misc.hh"
-
-#include <iostream>
+#include "base/trace.hh"
 
 namespace MipsISA
 {
@@ -96,7 +96,7 @@ restoreThread(TC *tc)
 
         // TODO: SET PC WITH AN EVENT INSTEAD OF INSTANTANEOUSLY
         tc->pcState(restartPC);
-        tc->activate(0);
+        tc->activate(Cycles(0));
 
         warn("%i: Restoring thread %i in %s @ PC %x",
                 curTick(), tc->threadId(), tc->getCpuPtr()->name(), restartPC);
@@ -113,23 +113,23 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
     int success = 0;
     for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) {
         TCBindReg tidTCBind =
-            tc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag, tid);
+            tc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base, tid);
         TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
 
         if (tidTCBind.curVPE == tcBind.curVPE) {
 
             TCStatusReg tidTCStatus =
                 tc->readRegOtherThread(MISCREG_TC_STATUS +
-                                       Ctrl_Base_DepTag,tid);
+                                       Misc_Reg_Base,tid);
 
             TCHaltReg tidTCHalt =
-                tc->readRegOtherThread(MISCREG_TC_HALT + Ctrl_Base_DepTag,tid);
+                tc->readRegOtherThread(MISCREG_TC_HALT + Misc_Reg_Base,tid);
 
             if (tidTCStatus.da == 1 && tidTCHalt.h == 0 &&
                 tidTCStatus.a == 0 && success == 0) {
 
                 tc->setRegOtherThread(MISCREG_TC_RESTART +
-                                      Ctrl_Base_DepTag, Rs, tid);
+                                      Misc_Reg_Base, Rs, tid);
                 tc->setRegOtherThread(Rd_bits, Rt, tid);
 
                 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
@@ -149,7 +149,7 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
                 tidTCStatus.asid = tcStatus.asid;
 
                 // Write Status Register
-                tc->setRegOtherThread(MISCREG_TC_STATUS + Ctrl_Base_DepTag,
+                tc->setRegOtherThread(MISCREG_TC_STATUS + Misc_Reg_Base,
                                       tidTCStatus, tid);
 
                 // Mark As Successful Fork
@@ -185,13 +185,13 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
 
         for (ThreadID tid = 0; tid < num_threads; tid++) {
             TCStatusReg tidTCStatus =
-                tc->readRegOtherThread(MISCREG_TC_STATUS + Ctrl_Base_DepTag,
+                tc->readRegOtherThread(MISCREG_TC_STATUS + Misc_Reg_Base,
                                        tid);
             TCHaltReg tidTCHalt =
-                tc->readRegOtherThread(MISCREG_TC_HALT + Ctrl_Base_DepTag,
+                tc->readRegOtherThread(MISCREG_TC_HALT + Misc_Reg_Base,
                                        tid);
             TCBindReg tidTCBind =
-                tc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag,
+                tc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base,
                                        tid);
 
             if (tidTCBind.curVPE == tcBind.curVPE &&