#ifndef __ARCH_MIPS_PAGETABLE_H__
#define __ARCH_MIPS_PAGETABLE_H__
-#include "arch/mips/isa_traits.hh"
-#include "arch/mips/utility.hh"
-#include "arch/mips/vtophys.hh"
-#include "config/full_system.hh"
+#include "base/misc.hh"
+#include "base/types.hh"
+#include "sim/serialize.hh"
namespace MipsISA {
- struct VAddr
+struct VAddr
+{
+};
+
+// ITB/DTB page table entry
+struct PTE
+{
+ Addr Mask;
+ Addr VPN;
+ uint8_t asid;
+
+ bool G;
+
+ /* Contents of Entry Lo0 */
+ Addr PFN0; // Physical Frame Number - Even
+ bool D0; // Even entry Dirty Bit
+ bool V0; // Even entry Valid Bit
+ uint8_t C0; // Cache Coherency Bits - Even
+
+ /* Contents of Entry Lo1 */
+ Addr PFN1; // Physical Frame Number - Odd
+ bool D1; // Odd entry Dirty Bit
+ bool V1; // Odd entry Valid Bit
+ uint8_t C1; // Cache Coherency Bits (3 bits)
+
+ /*
+ * The next few variables are put in as optimizations to reduce
+ * TLB lookup overheads. For a given Mask, what is the address shift
+ * amount, and what is the OffsetMask
+ */
+ int AddrShiftAmount;
+ int OffsetMask;
+
+ bool Valid() { return (V0 | V1); };
+ void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string §ion);
+};
+
+// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
+struct TlbEntry
+{
+ Addr _pageStart;
+ TlbEntry() {}
+ TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
+
+ Addr pageStart()
+ {
+ return _pageStart;
+ }
+
+ void
+ updateVaddr(Addr new_vaddr) {}
+
+ void serialize(std::ostream &os)
{
- static const int ImplBits = 43;
- static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
- static const Addr UnImplMask = ~ImplMask;
-
- VAddr(Addr a) : addr(a) {}
- Addr addr;
- operator Addr() const { return addr; }
- const VAddr &operator=(Addr a) { addr = a; return *this; }
-
- Addr vpn() const { return (addr & ImplMask) >> PageShift; }
- Addr page() const { return addr & Page_Mask; }
- Addr offset() const { return addr & PageOffset; }
-
- Addr level3() const
- { return MipsISA::PteAddr(addr >> PageShift); }
- Addr level2() const
- { return MipsISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
- Addr level1() const
- { return MipsISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
- };
-
- // ITB/DTB page table entry
- struct PTE
+ SERIALIZE_SCALAR(_pageStart);
+ }
+
+ void unserialize(Checkpoint *cp, const std::string §ion)
{
- Addr Mask; // What parts of the VAddr (from bits 28..11) should be used in translation (includes Mask and MaskX from PageMask)
- Addr VPN; // Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits 31..11 from EntryHi)
- uint8_t asid; // Address Space ID (8 bits) // Lower 8 bits of EntryHi
-
- bool G; // Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1 G bit
-
- /* Contents of Entry Lo0 */
- Addr PFN0; // Physical Frame Number - Even
- bool D0; // Even entry Dirty Bit
- bool V0; // Even entry Valid Bit
- uint8_t C0; // Cache Coherency Bits - Even
-
- /* Contents of Entry Lo1 */
- Addr PFN1; // Physical Frame Number - Odd
- bool D1; // Odd entry Dirty Bit
- bool V1; // Odd entry Valid Bit
- uint8_t C1; // Cache Coherency Bits (3 bits)
-
- /* The next few variables are put in as optimizations to reduce TLB lookup overheads */
- /* For a given Mask, what is the address shift amount, and what is the OffsetMask */
- int AddrShiftAmount;
- int OffsetMask;
-
- bool Valid() { return (V0 | V1);};
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string §ion);
- };
+ UNSERIALIZE_SCALAR(_pageStart);
+ }
+
+};
};
#endif // __ARCH_MIPS_PAGETABLE_H__