mips import pt. 1

[gem5.git] / src / arch / mips / regfile / float_regfile.hh

diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh
index ce5f1fdde51bea675bb1c675df77667977fd8ace..21c16c23804e6cace6de85ceb61ac2c5791a00ea 100644 (file)
--- a/src/arch/mips/regfile/float_regfile.hh
+++ b/src/arch/mips/regfile/float_regfile.hh
@@ -88,12 +88,9 @@ namespace MipsISA
 
       public:
 
-        void clear()
-        {
-            bzero(regs, sizeof(regs));
-        }
+        void clear() { bzero(&regs, sizeof(regs)); }
 
-        double readReg(int floatReg, int width)
+        double readReg(int floatReg, int width, unsigned tid = 0)
         {
             switch(width)
             {
@@ -115,7 +112,7 @@ namespace MipsISA
             }
         }
 
-        FloatRegBits readRegBits(int floatReg, int width)
+        FloatRegBits readRegBits(int floatReg, int width, unsigned tid = 0)
         {
             if (floatReg < NumFloatArchRegs - 1) {
                 switch(width)
@@ -137,8 +134,9 @@ namespace MipsISA
             }
         }
 
-        Fault setReg(int floatReg, const FloatRegVal &val, int width)
+        Fault setReg(int floatReg, const FloatRegVal &val, int width, unsigned tid = 0)
         {
+            using namespace std;
             switch(width)
             {
               case SingleWidth:
@@ -165,8 +163,9 @@ namespace MipsISA
             return NoFault;
         }
 
-        Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
+        Fault setRegBits(int floatReg, const FloatRegBits &val, int width, unsigned tid = 0)
         {
+            using namespace std;
 
             switch(width)
             {