#ifndef __ARCH_MIPS_REGISTERS_HH__
#define __ARCH_MIPS_REGISTERS_HH__
-#include "arch/mips/max_inst_regs.hh"
+#include "arch/mips/generated/max_inst_regs.hh"
#include "base/misc.hh"
#include "base/types.hh"
using MipsISAInst::MaxInstSrcRegs;
using MipsISAInst::MaxInstDestRegs;
+using MipsISAInst::MaxMiscDestRegs;
// Constants Related to the number of registers
const int NumIntArchRegs = 32;
const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
const uint32_t MIPS32_QNAN = 0x7fbfffff;
-const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);
+const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff);
enum FPControlRegNums {
- FIR = NumFloatArchRegs,
- FCCR,
- FEXR,
- FENR,
- FCSR
+ FLOATREG_FIR = NumFloatArchRegs,
+ FLOATREG_FCCR,
+ FLOATREG_FEXR,
+ FLOATREG_FENR,
+ FLOATREG_FCSR
};
enum FCSRBits {
};
enum MiscIntRegNums {
- LO = NumIntArchRegs,
- HI,
- DSPACX0,
- DSPLo1,
- DSPHi1,
- DSPACX1,
- DSPLo2,
- DSPHi2,
- DSPACX2,
- DSPLo3,
- DSPHi3,
- DSPACX3,
- DSPControl,
- DSPLo0 = LO,
- DSPHi0 = HI
+ INTREG_LO = NumIntArchRegs,
+ INTREG_DSP_LO0 = INTREG_LO,
+ INTREG_HI,
+ INTREG_DSP_HI0 = INTREG_HI,
+ INTREG_DSP_ACX0,
+ INTREG_DSP_LO1,
+ INTREG_DSP_HI1,
+ INTREG_DSP_ACX1,
+ INTREG_DSP_LO2,
+ INTREG_DSP_HI2,
+ INTREG_DSP_ACX2,
+ INTREG_DSP_LO3,
+ INTREG_DSP_HI3,
+ INTREG_DSP_ACX3,
+ INTREG_DSP_CONTROL
};
// semantically meaningful register indices
// The first set of names classify the CP0 names as Register Banks
// for easy indexing when using the 'RD + SEL' index combination
// in CP0 instructions.
-enum MiscRegTags {
- Index = Ctrl_Base_DepTag + 0, //Bank 0: 0 - 3
- MVPControl,
- MVPConf0,
- MVPConf1,
-
- CP0_Random = Ctrl_Base_DepTag + 8, //Bank 1: 8 - 15
- VPEControl,
- VPEConf0,
- VPEConf1,
- YQMask,
- VPESchedule,
- VPEScheFBack,
- VPEOpt,
-
- EntryLo0 = Ctrl_Base_DepTag + 16, //Bank 2: 16 - 23
- TCStatus,
- TCBind,
- TCRestart,
- TCHalt,
- TCContext,
- TCSchedule,
- TCScheFBack,
-
- EntryLo1 = Ctrl_Base_DepTag + 24, // Bank 3: 24
-
- Context = Ctrl_Base_DepTag + 32, // Bank 4: 32 - 33
- ContextConfig,
-
- PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41
- PageGrain = Ctrl_Base_DepTag + 41,
-
- Wired = Ctrl_Base_DepTag + 48, //Bank 6:48-55
- SRSConf0,
- SRSConf1,
- SRSConf2,
- SRSConf3,
- SRSConf4,
-
- HWRena = Ctrl_Base_DepTag + 56, //Bank 7: 56-63
-
- BadVAddr = Ctrl_Base_DepTag + 64, //Bank 8: 64-71
-
- Count = Ctrl_Base_DepTag + 72, //Bank 9: 72-79
-
- EntryHi = Ctrl_Base_DepTag + 80, //Bank 10: 80-87
-
- Compare = Ctrl_Base_DepTag + 88, //Bank 11: 88-95
-
- Status = Ctrl_Base_DepTag + 96, //Bank 12: 96-103
- IntCtl,
- SRSCtl,
- SRSMap,
-
- Cause = Ctrl_Base_DepTag + 104, //Bank 13: 104-111
-
- EPC = Ctrl_Base_DepTag + 112, //Bank 14: 112-119
-
- PRId = Ctrl_Base_DepTag + 120, //Bank 15: 120-127,
- EBase,
-
- Config = Ctrl_Base_DepTag + 128, //Bank 16: 128-135
- Config1,
- Config2,
- Config3,
- Config4,
- Config5,
- Config6,
- Config7,
-
-
- LLAddr = Ctrl_Base_DepTag + 136, //Bank 17: 136-143
-
- WatchLo0 = Ctrl_Base_DepTag + 144, //Bank 18: 144-151
- WatchLo1,
- WatchLo2,
- WatchLo3,
- WatchLo4,
- WatchLo5,
- WatchLo6,
- WatchLo7,
-
- WatchHi0 = Ctrl_Base_DepTag + 152, //Bank 19: 152-159
- WatchHi1,
- WatchHi2,
- WatchHi3,
- WatchHi4,
- WatchHi5,
- WatchHi6,
- WatchHi7,
-
- XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167
+enum MiscRegIndex{
+ MISCREG_INDEX = 0, //Bank 0: 0 - 3
+ MISCREG_MVP_CONTROL,
+ MISCREG_MVP_CONF0,
+ MISCREG_MVP_CONF1,
+
+ MISCREG_CP0_RANDOM = 8, //Bank 1: 8 - 15
+ MISCREG_VPE_CONTROL,
+ MISCREG_VPE_CONF0,
+ MISCREG_VPE_CONF1,
+ MISCREG_YQMASK,
+ MISCREG_VPE_SCHEDULE,
+ MISCREG_VPE_SCHEFBACK,
+ MISCREG_VPE_OPT,
+
+ MISCREG_ENTRYLO0 = 16, //Bank 2: 16 - 23
+ MISCREG_TC_STATUS,
+ MISCREG_TC_BIND,
+ MISCREG_TC_RESTART,
+ MISCREG_TC_HALT,
+ MISCREG_TC_CONTEXT,
+ MISCREG_TC_SCHEDULE,
+ MISCREG_TC_SCHEFBACK,
+
+ MISCREG_ENTRYLO1 = 24, // Bank 3: 24
+
+ MISCREG_CONTEXT = 32, // Bank 4: 32 - 33
+ MISCREG_CONTEXT_CONFIG,
+
+ MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41
+ MISCREG_PAGEGRAIN = 41,
+
+ MISCREG_WIRED = 48, //Bank 6:48-55
+ MISCREG_SRS_CONF0,
+ MISCREG_SRS_CONF1,
+ MISCREG_SRS_CONF2,
+ MISCREG_SRS_CONF3,
+ MISCREG_SRS_CONF4,
+
+ MISCREG_HWRENA = 56, //Bank 7: 56-63
+
+ MISCREG_BADVADDR = 64, //Bank 8: 64-71
+
+ MISCREG_COUNT = 72, //Bank 9: 72-79
+
+ MISCREG_ENTRYHI = 80, //Bank 10: 80-87
+
+ MISCREG_COMPARE = 88, //Bank 11: 88-95
+
+ MISCREG_STATUS = 96, //Bank 12: 96-103
+ MISCREG_INTCTL,
+ MISCREG_SRSCTL,
+ MISCREG_SRSMAP,
+
+ MISCREG_CAUSE = 104, //Bank 13: 104-111
+
+ MISCREG_EPC = 112, //Bank 14: 112-119
+
+ MISCREG_PRID = 120, //Bank 15: 120-127,
+ MISCREG_EBASE,
+
+ MISCREG_CONFIG = 128, //Bank 16: 128-135
+ MISCREG_CONFIG1,
+ MISCREG_CONFIG2,
+ MISCREG_CONFIG3,
+ MISCREG_CONFIG4,
+ MISCREG_CONFIG5,
+ MISCREG_CONFIG6,
+ MISCREG_CONFIG7,
+
+
+ MISCREG_LLADDR = 136, //Bank 17: 136-143
+
+ MISCREG_WATCHLO0 = 144, //Bank 18: 144-151
+ MISCREG_WATCHLO1,
+ MISCREG_WATCHLO2,
+ MISCREG_WATCHLO3,
+ MISCREG_WATCHLO4,
+ MISCREG_WATCHLO5,
+ MISCREG_WATCHLO6,
+ MISCREG_WATCHLO7,
+
+ MISCREG_WATCHHI0 = 152, //Bank 19: 152-159
+ MISCREG_WATCHHI1,
+ MISCREG_WATCHHI2,
+ MISCREG_WATCHHI3,
+ MISCREG_WATCHHI4,
+ MISCREG_WATCHHI5,
+ MISCREG_WATCHHI6,
+ MISCREG_WATCHHI7,
+
+ MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167
//Bank 21: 168-175
//Bank 22: 176-183
- Debug = Ctrl_Base_DepTag + 184, //Bank 23: 184-191
- TraceControl1,
- TraceControl2,
- UserTraceData,
- TraceBPC,
-
- DEPC = Ctrl_Base_DepTag + 192, //Bank 24: 192-199
-
- PerfCnt0 = Ctrl_Base_DepTag + 200, //Bank 25: 200-207
- PerfCnt1,
- PerfCnt2,
- PerfCnt3,
- PerfCnt4,
- PerfCnt5,
- PerfCnt6,
- PerfCnt7,
-
- ErrCtl = Ctrl_Base_DepTag + 208, //Bank 26: 208-215
-
- CacheErr0 = Ctrl_Base_DepTag + 216, //Bank 27: 216-223
- CacheErr1,
- CacheErr2,
- CacheErr3,
-
- TagLo0 = Ctrl_Base_DepTag + 224, //Bank 28: 224-231
- DataLo1,
- TagLo2,
- DataLo3,
- TagLo4,
- DataLo5,
- TagLo6,
- DataLo7,
-
- TagHi0 = Ctrl_Base_DepTag + 232, //Bank 29: 232-239
- DataHi1,
- TagHi2,
- DataHi3,
- TagHi4,
- DataHi5,
- TagHi6,
- DataHi7,
-
-
- ErrorEPC = Ctrl_Base_DepTag + 240, //Bank 30: 240-247
-
- DESAVE = Ctrl_Base_DepTag + 248, //Bank 31: 248-256
-
- LLFlag = Ctrl_Base_DepTag + 257,
-
- NumControlRegs
+ MISCREG_DEBUG = 184, //Bank 23: 184-191
+ MISCREG_TRACE_CONTROL1,
+ MISCREG_TRACE_CONTROL2,
+ MISCREG_USER_TRACE_DATA,
+ MISCREG_TRACE_BPC,
+
+ MISCREG_DEPC = 192, //Bank 24: 192-199
+
+ MISCREG_PERFCNT0 = 200, //Bank 25: 200-207
+ MISCREG_PERFCNT1,
+ MISCREG_PERFCNT2,
+ MISCREG_PERFCNT3,
+ MISCREG_PERFCNT4,
+ MISCREG_PERFCNT5,
+ MISCREG_PERFCNT6,
+ MISCREG_PERFCNT7,
+
+ MISCREG_ERRCTL = 208, //Bank 26: 208-215
+
+ MISCREG_CACHEERR0 = 216, //Bank 27: 216-223
+ MISCREG_CACHEERR1,
+ MISCREG_CACHEERR2,
+ MISCREG_CACHEERR3,
+
+ MISCREG_TAGLO0 = 224, //Bank 28: 224-231
+ MISCREG_DATALO1,
+ MISCREG_TAGLO2,
+ MISCREG_DATALO3,
+ MISCREG_TAGLO4,
+ MISCREG_DATALO5,
+ MISCREG_TAGLO6,
+ MISCREG_DATALO7,
+
+ MISCREG_TAGHI0 = 232, //Bank 29: 232-239
+ MISCREG_DATAHI1,
+ MISCREG_TAGHI2,
+ MISCREG_DATAHI3,
+ MISCREG_TAGHI4,
+ MISCREG_DATAHI5,
+ MISCREG_TAGHI6,
+ MISCREG_DATAHI7,
+
+
+ MISCREG_ERROR_EPC = 240, //Bank 30: 240-247
+
+ MISCREG_DESAVE = 248, //Bank 31: 248-256
+
+ MISCREG_LLFLAG = 257,
+ MISCREG_TP_VALUE,
+
+ MISCREG_NUMREGS
};
const int TotalDataRegs = NumIntRegs + NumFloatRegs;
-const int NumMiscRegs = NumControlRegs;
+const int NumMiscRegs = MISCREG_NUMREGS;
+const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
projects / gem5.git / blobdiff