sim: Move the BaseTLB to src/arch/generic/

[gem5.git] / src / arch / mips / tlb.cc

diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 52e13dfc36225281d119145abbb280cf16b66729..b43797541491e14caeb85588d4950939ad772e3e 100644 (file)
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -29,6 +29,8 @@
  * Authors: Nathan Binkert
  *          Steve Reinhardt
  *          Jaidev Patwardhan
+ *          Zhengxing Li
+ *          Deyuan Guo
  */
 
 #include <string>
@@ -57,21 +59,6 @@ using namespace MipsISA;
 //  MIPS TLB
 //
 
-static inline mode_type
-getOperatingMode(MiscReg Stat)
-{
-    if ((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0) {
-        return mode_kernel;
-    } else if ((Stat & 0x18) == 0x8) {
-        return mode_supervisor;
-    } else if ((Stat & 0x18) == 0x10) {
-        return mode_user;
-    } else {
-        return mode_number;
-    }
-}
-
-
 TLB::TLB(const Params *p)
     : BaseTLB(p), size(p->size), nlu(0)
 {
@@ -129,7 +116,6 @@ int
 TLB::probeEntry(Addr vpn, uint8_t asn) const
 {
     // assume not found...
-    PTE *retval = NULL;
     int Ind = -1;
     PageTable::const_iterator i = lookupTable.find(vpn);
     if (i != lookupTable.end()) {
@@ -144,7 +130,6 @@ TLB::probeEntry(Addr vpn, uint8_t asn) const
             if (((vpn & InvMask) == (VPN & InvMask)) &&
                     (pte->G  || (asn == pte->asid))) {
                 // We have a VPN + ASID Match
-                retval = pte;
                 Ind = index;
                 break;
             }
@@ -184,7 +169,7 @@ TLB::insertAt(PTE &pte, unsigned Index, int _smallPages)
                  (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
                 ((pte.PFN1 <<6) | (pte.C1 << 3) |
                  (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
-        if (table[Index].V0 == true || table[Index].V1 == true) {
+        if (table[Index].V0 || table[Index].V1) {
             // Previous entry is valid
             PageTable::iterator i = lookupTable.find(table[Index].VPN);
             lookupTable.erase(i);
@@ -295,45 +280,31 @@ TLB::regStats()
 Fault
 TLB::translateInst(RequestPtr req, ThreadContext *tc)
 {
-    if (!FullSystem) {
-        Process * p = tc->getProcessPtr();
+    if (FullSystem)
+        panic("translateInst not implemented in MIPS.\n");
 
-        Fault fault = p->pTable->translate(req);
-        if (fault != NoFault)
-            return fault;
+    Process * p = tc->getProcessPtr();
 
-        return NoFault;
-    } else {
-        panic("translateInst not implemented in MIPS.\n");
-    }
+    Fault fault = p->pTable->translate(req);
+    if (fault != NoFault)
+        return fault;
+
+    return NoFault;
 }
 
 Fault
 TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
 {
-    if (!FullSystem) {
-        //@TODO: This should actually use TLB instead of going directly
-        //       to the page table in syscall mode.
-        /**
-         * Check for alignment faults
-         */
-        if (req->getVaddr() & (req->getSize() - 1)) {
-            DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
-                    req->getSize());
-            return new AddressErrorFault(req->getVaddr(), write);
-        }
-
+    if (FullSystem)
+        panic("translateData not implemented in MIPS.\n");
 
-        Process * p = tc->getProcessPtr();
+    Process * p = tc->getProcessPtr();
 
-        Fault fault = p->pTable->translate(req);
-        if (fault != NoFault)
-            return fault;
+    Fault fault = p->pTable->translate(req);
+    if (fault != NoFault)
+        return fault;
 
-        return NoFault;
-    } else {
-        panic("translateData not implemented in MIPS.\n");
-    }
+    return NoFault;
 }
 
 Fault
@@ -353,6 +324,19 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 }
 
+Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+    panic("Not implemented\n");
+    return NoFault;
+}
+
+Fault
+TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+{
+    return NoFault;
+}
+
 
 MipsISA::PTE &
 TLB::index(bool advance)