arm: Clean up and document decoder API

[gem5.git] / src / arch / mips / tlb.cc

diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index cd6d47d1e26a75c0ec3aa1cb90f44b9ef3d307f3..b43797541491e14caeb85588d4950939ad772e3e 100644 (file)
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -59,21 +59,6 @@ using namespace MipsISA;
 //  MIPS TLB
 //
 
-static inline mode_type
-getOperatingMode(MiscReg Stat)
-{
-    if ((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0) {
-        return mode_kernel;
-    } else if ((Stat & 0x18) == 0x8) {
-        return mode_supervisor;
-    } else if ((Stat & 0x18) == 0x10) {
-        return mode_user;
-    } else {
-        return mode_number;
-    }
-}
-
-
 TLB::TLB(const Params *p)
     : BaseTLB(p), size(p->size), nlu(0)
 {
@@ -184,7 +169,7 @@ TLB::insertAt(PTE &pte, unsigned Index, int _smallPages)
                  (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
                 ((pte.PFN1 <<6) | (pte.C1 << 3) |
                  (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
-        if (table[Index].V0 == true || table[Index].V1 == true) {
+        if (table[Index].V0 || table[Index].V1) {
             // Previous entry is valid
             PageTable::iterator i = lookupTable.find(table[Index].VPN);
             lookupTable.erase(i);
@@ -339,6 +324,19 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 }
 
+Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+    panic("Not implemented\n");
+    return NoFault;
+}
+
+Fault
+TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+{
+    return NoFault;
+}
+
 
 MipsISA::PTE &
 TLB::index(bool advance)