#include <map>
+#include "arch/generic/tlb.hh"
#include "arch/mips/isa_traits.hh"
+#include "arch/mips/pagetable.hh"
#include "arch/mips/utility.hh"
#include "arch/mips/vtophys.hh"
-#include "arch/mips/pagetable.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
-#include "params/MipsDTB.hh"
-#include "params/MipsITB.hh"
-#include "sim/faults.hh"
-#include "sim/tlb.hh"
+#include "params/MipsTLB.hh"
#include "sim/sim_object.hh"
class ThreadContext;
simply create an ITLB and DTLB that will point to the real TLB */
namespace MipsISA {
-// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
-struct TlbEntry
-{
- Addr _pageStart;
- TlbEntry() {}
- TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
-
- Addr pageStart()
- {
- return _pageStart;
- }
-
- void
- updateVaddr(Addr new_vaddr) {}
-
- void serialize(std::ostream &os)
- {
- SERIALIZE_SCALAR(_pageStart);
- }
-
- void unserialize(Checkpoint *cp, const std::string §ion)
- {
- UNSERIALIZE_SCALAR(_pageStart);
- }
-
-};
-
class TLB : public BaseTLB
{
protected:
void nextnlu() { if (++nlu >= size) nlu = 0; }
MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
- mutable Stats::Scalar<> read_hits;
- mutable Stats::Scalar<> read_misses;
- mutable Stats::Scalar<> read_acv;
- mutable Stats::Scalar<> read_accesses;
- mutable Stats::Scalar<> write_hits;
- mutable Stats::Scalar<> write_misses;
- mutable Stats::Scalar<> write_acv;
- mutable Stats::Scalar<> write_accesses;
+ mutable Stats::Scalar read_hits;
+ mutable Stats::Scalar read_misses;
+ mutable Stats::Scalar read_acv;
+ mutable Stats::Scalar read_accesses;
+ mutable Stats::Scalar write_hits;
+ mutable Stats::Scalar write_misses;
+ mutable Stats::Scalar write_acv;
+ mutable Stats::Scalar write_accesses;
Stats::Formula hits;
Stats::Formula misses;
- Stats::Formula invalids;
Stats::Formula accesses;
public:
int probeEntry(Addr vpn,uint8_t) const;
MipsISA::PTE *getEntry(unsigned) const;
virtual ~TLB();
+
+ void takeOverFrom(BaseTLB *otlb) {}
+
int smallPages;
int getsize() const { return size; }
void unserialize(Checkpoint *cp, const std::string §ion);
void regStats();
-};
-
-class ITB : public TLB {
- public:
- typedef MipsTLBParams Params;
- ITB(const Params *p);
- Fault translateAtomic(RequestPtr req, ThreadContext *tc);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation);
-};
+ Translation *translation, Mode mode);
-class DTB : public TLB {
- public:
- typedef MipsTLBParams Params;
- DTB(const Params *p);
-
- Fault translateAtomic(RequestPtr req, ThreadContext *tc,
- bool write = false);
- void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool write = false);
-};
-
-class UTB : public ITB, public DTB {
- public:
- typedef MipsTLBParams Params;
- UTB(const Params *p);
+ /** Function stub for CheckerCPU compilation issues. MIPS does not
+ * support the Checker model at the moment.
+ */
+ Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+ Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
+ private:
+ Fault translateInst(RequestPtr req, ThreadContext *tc);
+ Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
};
}