sim: Move the BaseTLB to src/arch/generic/

[gem5.git] / src / arch / mips / tlb.hh

diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 225e207dc55f236dedadcb54c0d1c2024426a5e8..c7cd5e63189c8eacd64682c9c8e5f30d69791779 100644 (file)
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -37,6 +37,7 @@
 
 #include <map>
 
+#include "arch/generic/tlb.hh"
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/pagetable.hh"
 #include "arch/mips/utility.hh"
@@ -45,7 +46,6 @@
 #include "mem/request.hh"
 #include "params/MipsTLB.hh"
 #include "sim/sim_object.hh"
-#include "sim/tlb.hh"
 
 class ThreadContext;