X86: Define a noop ExtMachInst.

[gem5.git] / src / arch / mips / tlb.hh

diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index d6f9ac101f8ad0d810844dc7258db0a4aa75537c..e301cf666a56db9e9a4a1d57c7344dbeb6ccceb1 100644 (file)
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -43,8 +43,7 @@
 #include "arch/mips/pagetable.hh"
 #include "base/statistics.hh"
 #include "mem/request.hh"
-#include "params/MipsDTB.hh"
-#include "params/MipsITB.hh"
+#include "params/MipsTLB.hh"
 #include "sim/faults.hh"
 #include "sim/tlb.hh"
 #include "sim/sim_object.hh"
@@ -68,6 +67,9 @@ struct TlbEntry
         return _pageStart;
     }
 
+    void
+    updateVaddr(Addr new_vaddr) {}
+    
     void serialize(std::ostream &os)
     {
         SERIALIZE_SCALAR(_pageStart);
@@ -80,30 +82,29 @@ struct TlbEntry
 
 };
 
-class TLB : public SimObject
+class TLB : public BaseTLB
 {
   protected:
     typedef std::multimap<Addr, int> PageTable;
-    PageTable lookupTable;     // Quick lookup into page table
+    PageTable lookupTable;      // Quick lookup into page table
 
-    MipsISA::PTE *table;       // the Page Table
-    int size;                  // TLB Size
-    int nlu;                   // not last used entry (for replacement)
+    MipsISA::PTE *table;        // the Page Table
+    int size;                   // TLB Size
+    int nlu;                    // not last used entry (for replacement)
 
     void nextnlu() { if (++nlu >= size) nlu = 0; }
     MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
 
-    mutable Stats::Scalar<> read_hits;
-    mutable Stats::Scalar<> read_misses;
-    mutable Stats::Scalar<> read_acv;
-    mutable Stats::Scalar<> read_accesses;
-    mutable Stats::Scalar<> write_hits;
-    mutable Stats::Scalar<> write_misses;
-    mutable Stats::Scalar<> write_acv;
-    mutable Stats::Scalar<> write_accesses;
+    mutable Stats::Scalar read_hits;
+    mutable Stats::Scalar read_misses;
+    mutable Stats::Scalar read_acv;
+    mutable Stats::Scalar read_accesses;
+    mutable Stats::Scalar write_hits;
+    mutable Stats::Scalar write_misses;
+    mutable Stats::Scalar write_acv;
+    mutable Stats::Scalar write_accesses;
     Stats::Formula hits;
     Stats::Formula misses;
-    Stats::Formula invalids;
     Stats::Formula accesses;
 
   public:
@@ -120,6 +121,10 @@ class TLB : public SimObject
     void insert(Addr vaddr, MipsISA::PTE &pte);
     void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
     void flushAll();
+    void demapPage(Addr vaddr, uint64_t asn)
+    {
+        panic("demapPage unimplemented.\n");
+    }
 
     // static helper functions... really
     static bool validVirtualAddress(Addr vaddr);
@@ -131,29 +136,14 @@ class TLB : public SimObject
     void unserialize(Checkpoint *cp, const std::string &section);
 
     void regStats();
-};
-
-class ITB : public TLB {
-  public:
-    typedef MipsTLBParams Params;
-    ITB(const Params *p);
-
-    Fault translate(RequestPtr &req, ThreadContext *tc);
-};
 
-class DTB : public TLB {
-  public:
-    typedef MipsTLBParams Params;
-    DTB(const Params *p);
-
-    Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false);
-};
-
-class UTB : public ITB, public DTB {
-  public:
-    typedef MipsTLBParams Params;
-    UTB(const Params *p);
+    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+            Translation *translation, Mode mode);
 
+  private:
+    Fault translateInst(RequestPtr req, ThreadContext *tc);
+    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
 };
 
 }