/*
+ * Copyright (c) 2001-2005 The Regents of The University of Michigan
* Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Jaidev Patwardhan
+ * Authors: Nathan Binkert
+ * Steve Reinhardt
+ * Jaidev Patwardhan
+ * Korey Sewell
*/
#ifndef __ARCH_MIPS_TLB_HH__
#include <map>
#include "arch/mips/isa_traits.hh"
+#include "arch/mips/pagetable.hh"
#include "arch/mips/utility.hh"
#include "arch/mips/vtophys.hh"
-#include "arch/mips/pagetable.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
-#include "params/MipsDTB.hh"
-#include "params/MipsITB.hh"
-#include "sim/faults.hh"
-#include "sim/tlb.hh"
+#include "params/MipsTLB.hh"
+#include "sim/fault_fwd.hh"
#include "sim/sim_object.hh"
+#include "sim/tlb.hh"
class ThreadContext;
simply create an ITLB and DTLB that will point to the real TLB */
namespace MipsISA {
-// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
-struct TlbEntry
-{
- Addr _pageStart;
- TlbEntry() {}
- TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
-
- Addr pageStart()
- {
- return _pageStart;
- }
-
- void serialize(std::ostream &os)
- {
- SERIALIZE_SCALAR(_pageStart);
- }
-
- void unserialize(Checkpoint *cp, const std::string §ion)
- {
- UNSERIALIZE_SCALAR(_pageStart);
- }
-
-};
-
-class TLB : public SimObject
+class TLB : public BaseTLB
{
protected:
typedef std::multimap<Addr, int> PageTable;
- PageTable lookupTable; // Quick lookup into page table
+ PageTable lookupTable; // Quick lookup into page table
- MipsISA::PTE *table; // the Page Table
- int size; // TLB Size
- int nlu; // not last used entry (for replacement)
+ MipsISA::PTE *table; // the Page Table
+ int size; // TLB Size
+ int nlu; // not last used entry (for replacement)
void nextnlu() { if (++nlu >= size) nlu = 0; }
MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
- mutable Stats::Scalar<> read_hits;
- mutable Stats::Scalar<> read_misses;
- mutable Stats::Scalar<> read_acv;
- mutable Stats::Scalar<> read_accesses;
- mutable Stats::Scalar<> write_hits;
- mutable Stats::Scalar<> write_misses;
- mutable Stats::Scalar<> write_acv;
- mutable Stats::Scalar<> write_accesses;
+ mutable Stats::Scalar read_hits;
+ mutable Stats::Scalar read_misses;
+ mutable Stats::Scalar read_acv;
+ mutable Stats::Scalar read_accesses;
+ mutable Stats::Scalar write_hits;
+ mutable Stats::Scalar write_misses;
+ mutable Stats::Scalar write_acv;
+ mutable Stats::Scalar write_accesses;
Stats::Formula hits;
Stats::Formula misses;
- Stats::Formula invalids;
Stats::Formula accesses;
public:
void insert(Addr vaddr, MipsISA::PTE &pte);
void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
void flushAll();
+ void demapPage(Addr vaddr, uint64_t asn)
+ {
+ panic("demapPage unimplemented.\n");
+ }
// static helper functions... really
static bool validVirtualAddress(Addr vaddr);
void unserialize(Checkpoint *cp, const std::string §ion);
void regStats();
-};
-class ITB : public TLB {
- public:
- typedef MipsTLBParams Params;
- ITB(const Params *p);
-
- Fault translate(RequestPtr &req, ThreadContext *tc);
-};
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
+ void translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, Mode mode);
-class DTB : public TLB {
- public:
- typedef MipsTLBParams Params;
- DTB(const Params *p);
-
- Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false);
-};
-
-class UTB : public ITB, public DTB {
- public:
- typedef MipsTLBParams Params;
- UTB(const Params *p);
+ /** Function stub for CheckerCPU compilation issues. MIPS does not
+ * support the Checker model at the moment.
+ */
+ Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+ private:
+ Fault translateInst(RequestPtr req, ThreadContext *tc);
+ Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
};
}