syscall emulation: Enabled getrlimit and getrusage for x86.

[gem5.git] / src / arch / mips / tlb.hh

diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index cb2e434cb6a562d753b70dcb9578a54299899547..e949d16d9a55363c7a5a889a132edb4ed7eac5c0 100644 (file)
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -38,15 +38,15 @@
 #include <map>
 
 #include "arch/mips/isa_traits.hh"
+#include "arch/mips/pagetable.hh"
 #include "arch/mips/utility.hh"
 #include "arch/mips/vtophys.hh"
-#include "arch/mips/pagetable.hh"
 #include "base/statistics.hh"
 #include "mem/request.hh"
 #include "params/MipsTLB.hh"
-#include "sim/fault.hh"
-#include "sim/tlb.hh"
+#include "sim/fault_fwd.hh"
 #include "sim/sim_object.hh"
+#include "sim/tlb.hh"
 
 class ThreadContext;
 
@@ -55,33 +55,6 @@ class ThreadContext;
    simply create an ITLB and DTLB that will point to the real TLB */
 namespace MipsISA {
 
-// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
-struct TlbEntry
-{
-    Addr _pageStart;
-    TlbEntry() {}
-    TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
-
-    Addr pageStart()
-    {
-        return _pageStart;
-    }
-
-    void
-    updateVaddr(Addr new_vaddr) {}
-    
-    void serialize(std::ostream &os)
-    {
-        SERIALIZE_SCALAR(_pageStart);
-    }
-
-    void unserialize(Checkpoint *cp, const std::string &section)
-    {
-        UNSERIALIZE_SCALAR(_pageStart);
-    }
-
-};
-
 class TLB : public BaseTLB
 {
   protected:
@@ -141,6 +114,11 @@ class TLB : public BaseTLB
     void translateTiming(RequestPtr req, ThreadContext *tc,
             Translation *translation, Mode mode);
 
+    /** Function stub for CheckerCPU compilation issues. MIPS does not
+     *  support the Checker model at the moment.
+     */
+    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+
   private:
     Fault translateInst(RequestPtr req, ThreadContext *tc);
     Fault translateData(RequestPtr req, ThreadContext *tc, bool write);