syscall emulation: Enabled getrlimit and getrusage for x86.

[gem5.git] / src / arch / mips / tlb.hh

diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index feb2509c561c9da47694d62f6a7514a418c1b6e9..e949d16d9a55363c7a5a889a132edb4ed7eac5c0 100644 (file)
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -38,16 +38,15 @@
 #include <map>
 
 #include "arch/mips/isa_traits.hh"
+#include "arch/mips/pagetable.hh"
 #include "arch/mips/utility.hh"
 #include "arch/mips/vtophys.hh"
-#include "arch/mips/pagetable.hh"
 #include "base/statistics.hh"
 #include "mem/request.hh"
-#include "params/MipsDTB.hh"
-#include "params/MipsITB.hh"
-#include "sim/faults.hh"
-#include "sim/tlb.hh"
+#include "params/MipsTLB.hh"
+#include "sim/fault_fwd.hh"
 #include "sim/sim_object.hh"
+#include "sim/tlb.hh"
 
 class ThreadContext;
 
@@ -56,30 +55,6 @@ class ThreadContext;
    simply create an ITLB and DTLB that will point to the real TLB */
 namespace MipsISA {
 
-// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
-struct TlbEntry
-{
-    Addr _pageStart;
-    TlbEntry() {}
-    TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
-
-    Addr pageStart()
-    {
-        return _pageStart;
-    }
-
-    void serialize(std::ostream &os)
-    {
-        SERIALIZE_SCALAR(_pageStart);
-    }
-
-    void unserialize(Checkpoint *cp, const std::string &section)
-    {
-        UNSERIALIZE_SCALAR(_pageStart);
-    }
-
-};
-
 class TLB : public BaseTLB
 {
   protected:
@@ -93,17 +68,16 @@ class TLB : public BaseTLB
     void nextnlu() { if (++nlu >= size) nlu = 0; }
     MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
 
-    mutable Stats::Scalar<> read_hits;
-    mutable Stats::Scalar<> read_misses;
-    mutable Stats::Scalar<> read_acv;
-    mutable Stats::Scalar<> read_accesses;
-    mutable Stats::Scalar<> write_hits;
-    mutable Stats::Scalar<> write_misses;
-    mutable Stats::Scalar<> write_acv;
-    mutable Stats::Scalar<> write_accesses;
+    mutable Stats::Scalar read_hits;
+    mutable Stats::Scalar read_misses;
+    mutable Stats::Scalar read_acv;
+    mutable Stats::Scalar read_accesses;
+    mutable Stats::Scalar write_hits;
+    mutable Stats::Scalar write_misses;
+    mutable Stats::Scalar write_acv;
+    mutable Stats::Scalar write_accesses;
     Stats::Formula hits;
     Stats::Formula misses;
-    Stats::Formula invalids;
     Stats::Formula accesses;
 
   public:
@@ -135,29 +109,19 @@ class TLB : public BaseTLB
     void unserialize(Checkpoint *cp, const std::string &section);
 
     void regStats();
-};
-
-class ITB : public TLB {
-  public:
-    typedef MipsTLBParams Params;
-    ITB(const Params *p);
-
-    Fault translate(RequestPtr &req, ThreadContext *tc);
-};
 
-class DTB : public TLB {
-  public:
-    typedef MipsTLBParams Params;
-    DTB(const Params *p);
+    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+            Translation *translation, Mode mode);
 
-    Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false);
-};
-
-class UTB : public ITB, public DTB {
-  public:
-    typedef MipsTLBParams Params;
-    UTB(const Params *p);
+    /** Function stub for CheckerCPU compilation issues. MIPS does not
+     *  support the Checker model at the moment.
+     */
+    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
 
+  private:
+    Fault translateInst(RequestPtr req, ThreadContext *tc);
+    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
 };
 
 }