cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.

[gem5.git] / src / arch / mips / tlb.hh

diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index e949d16d9a55363c7a5a889a132edb4ed7eac5c0..fdd590e85064cf76852336c377604f8b3c40f8c9 100644 (file)
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -118,6 +118,7 @@ class TLB : public BaseTLB
      *  support the Checker model at the moment.
      */
     Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+    Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
 
   private:
     Fault translateInst(RequestPtr req, ThreadContext *tc);