#include <map>
#include "arch/mips/isa_traits.hh"
+#include "arch/mips/pagetable.hh"
#include "arch/mips/utility.hh"
#include "arch/mips/vtophys.hh"
-#include "arch/mips/pagetable.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
#include "params/MipsTLB.hh"
-#include "sim/faults.hh"
-#include "sim/tlb.hh"
+#include "sim/fault_fwd.hh"
#include "sim/sim_object.hh"
+#include "sim/tlb.hh"
class ThreadContext;
simply create an ITLB and DTLB that will point to the real TLB */
namespace MipsISA {
-// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
-struct TlbEntry
-{
- Addr _pageStart;
- TlbEntry() {}
- TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
-
- Addr pageStart()
- {
- return _pageStart;
- }
-
- void
- updateVaddr(Addr new_vaddr) {}
-
- void serialize(std::ostream &os)
- {
- SERIALIZE_SCALAR(_pageStart);
- }
-
- void unserialize(Checkpoint *cp, const std::string §ion)
- {
- UNSERIALIZE_SCALAR(_pageStart);
- }
-
-};
-
class TLB : public BaseTLB
{
protected:
mutable Stats::Scalar write_accesses;
Stats::Formula hits;
Stats::Formula misses;
- Stats::Formula invalids;
Stats::Formula accesses;
public:
void regStats();
- Fault translateAtomic(RequestPtr req, ThreadContext *tc,
- bool write=false, bool execute=false);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool write=false, bool execute=false);
+ Translation *translation, Mode mode);
+
+ /** Function stub for CheckerCPU compilation issues. MIPS does not
+ * support the Checker model at the moment.
+ */
+ Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+ Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
private:
Fault translateInst(RequestPtr req, ThreadContext *tc);