syscall emulation: Enabled getrlimit and getrusage for x86.

[gem5.git] / src / arch / mips / types.hh

diff --git a/src/arch/mips/types.hh b/src/arch/mips/types.hh
index b459d9e146d03cbc4c605c6c9cd46aa97fd4b409..c549e81ca768819e8e3506a88d2d79305f736ba8 100644 (file)
--- a/src/arch/mips/types.hh
+++ b/src/arch/mips/types.hh
@@ -31,77 +31,77 @@
 #ifndef __ARCH_MIPS_TYPES_HH__
 #define __ARCH_MIPS_TYPES_HH__
 
-#include "sim/host.hh"
+#include "arch/generic/types.hh"
+#include "base/types.hh"
 
 namespace MipsISA
 {
-    typedef uint32_t MachInst;
-    typedef uint64_t ExtMachInst;
-    typedef uint16_t  RegIndex;
-
-    typedef uint32_t IntReg;
-    typedef uint64_t LargestRead;
-
-
-    // floating point register file entry type
-    typedef uint32_t FloatReg32;
-    typedef uint64_t FloatReg64;
-    typedef uint64_t FloatRegBits;
-
-    typedef double FloatRegVal;
-    typedef double FloatReg;
-
-    // cop-0/cop-1 system control register
-    typedef uint64_t MiscReg;
-
-    typedef union {
-        IntReg   intreg;
-        FloatReg fpreg;
-        MiscReg  ctrlreg;
-    } AnyReg;
-
-    //used in FP convert & round function
-    enum ConvertType{
-        SINGLE_TO_DOUBLE,
-        SINGLE_TO_WORD,
-        SINGLE_TO_LONG,
-
-        DOUBLE_TO_SINGLE,
-        DOUBLE_TO_WORD,
-        DOUBLE_TO_LONG,
-
-        LONG_TO_SINGLE,
-        LONG_TO_DOUBLE,
-        LONG_TO_WORD,
-        LONG_TO_PS,
-
-        WORD_TO_SINGLE,
-        WORD_TO_DOUBLE,
-        WORD_TO_LONG,
-        WORD_TO_PS,
-
-        PL_TO_SINGLE,
-        PU_TO_SINGLE
-    };
-
-    //used in FP convert & round function
-    enum RoundMode{
-        RND_ZERO,
-        RND_DOWN,
-        RND_UP,
-        RND_NEAREST
-   };
+
+typedef uint32_t MachInst;
+typedef uint64_t ExtMachInst;
+
+typedef GenericISA::DelaySlotPCState<MachInst> PCState;
+
+typedef uint64_t LargestRead;
+
+//used in FP convert & round function
+enum ConvertType{
+    SINGLE_TO_DOUBLE,
+    SINGLE_TO_WORD,
+    SINGLE_TO_LONG,
+
+    DOUBLE_TO_SINGLE,
+    DOUBLE_TO_WORD,
+    DOUBLE_TO_LONG,
+
+    LONG_TO_SINGLE,
+    LONG_TO_DOUBLE,
+    LONG_TO_WORD,
+    LONG_TO_PS,
+
+    WORD_TO_SINGLE,
+    WORD_TO_DOUBLE,
+    WORD_TO_LONG,
+    WORD_TO_PS,
+
+    PL_TO_SINGLE,
+    PU_TO_SINGLE
+};
+
+//used in FP convert & round function
+enum RoundMode{
+    RND_ZERO,
+    RND_DOWN,
+    RND_UP,
+    RND_NEAREST
+};
 
 struct CoreSpecific {
-      /* Note: It looks like it will be better to allow simulator users
-         to specify the values of individual variables instead of requiring
-         users to define the values of entire registers
-         Especially since a lot of these variables can be created from other
-         user parameters  (cache descriptions)
-                                               -jpp
-      */
+    CoreSpecific()
+        : CP0_IntCtl_IPTI(0), CP0_IntCtl_IPPCI(0), CP0_SrsCtl_HSS(0),
+          CP0_PRId_CompanyOptions(0), CP0_PRId_CompanyID(0),
+          CP0_PRId_ProcessorID(0), CP0_PRId_Revision(0),
+          CP0_EBase_CPUNum(0), CP0_Config_BE(0), CP0_Config_AT(0),
+          CP0_Config_AR(0), CP0_Config_MT(0), CP0_Config_VI(0),
+          CP0_Config1_M(0), CP0_Config1_MMU(0), CP0_Config1_IS(0),
+          CP0_Config1_IL(0), CP0_Config1_IA(0), CP0_Config1_DS(0),
+          CP0_Config1_DL(0), CP0_Config1_DA(0), CP0_Config1_C2(false),
+          CP0_Config1_MD(false), CP0_Config1_PC(false), CP0_Config1_WR(false),
+          CP0_Config1_CA(false), CP0_Config1_EP(false), CP0_Config1_FP(false),
+          CP0_Config2_M(false), CP0_Config2_TU(0), CP0_Config2_TS(0),
+          CP0_Config2_TL(0), CP0_Config2_TA(0), CP0_Config2_SU(0),
+          CP0_Config2_SS(0), CP0_Config2_SL(0), CP0_Config2_SA(0),
+          CP0_Config3_M(false), CP0_Config3_DSPP(false), CP0_Config3_LPA(false),
+          CP0_Config3_VEIC(false), CP0_Config3_VInt(false),
+          CP0_Config3_SP(false), CP0_Config3_MT(false), CP0_Config3_SM(false),
+          CP0_Config3_TL(false), CP0_WatchHi_M(false), CP0_PerfCtr_M(false),
+          CP0_PerfCtr_W(false), CP0_PRId(0), CP0_Config(0), CP0_Config1(0),
+          CP0_Config2(0), CP0_Config3(0)
+    { }
+
       // MIPS CP0 State - First individual variables
-      // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM, Volume III (PRA)
+      // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM,
+      // Volume III (PRA)
       unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt
       unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt
       unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set
@@ -109,7 +109,8 @@ struct CoreSpecific {
       unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS)
       unsigned CP0_PRId_ProcessorID; // Page 105
       unsigned CP0_PRId_Revision; // Page 105
-      unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor system
+      unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor
+                                 //system
       unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode
       unsigned CP0_Config_AT; //Page 109
       unsigned CP0_Config_AR; //Page 109
@@ -163,5 +164,4 @@ struct CoreSpecific {
 };
 
 } // namespace MipsISA
-
 #endif