X86: Use IsSquashAfter if an instruction could affect fetch translation.

[gem5.git] / src / arch / mips / utility.cc

diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 36cf76c67b0da29e15ab377b7bf153c37c130933..37f71416f8f68131b1d782825fb03ad1f6f83743 100644 (file)
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -28,16 +28,19 @@
  * Authors: Korey Sewell
  */
 
+#include <cmath>
+
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/utility.hh"
+#include "base/bitfield.hh"
+#include "base/misc.hh"
 #include "config/full_system.hh"
-#include "cpu/thread_context.hh"
 #include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
 #include "sim/serialize.hh"
-#include "base/bitfield.hh"
-#include "base/misc.hh"
 
 #if FULL_SYSTEM
+#include "arch/mips/registers.hh"
 #include "arch/mips/vtophys.hh"
 #include "mem/vport.hh"
 #endif
@@ -49,19 +52,19 @@ using namespace std;
 namespace MipsISA {
 
 uint64_t
-getArgument(ThreadContext *tc, int number, bool fp)
+getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
 {
 #if FULL_SYSTEM
-    if (number < NumArgumentRegs) {
+    if (number < 4) {
         if (fp)
-            return tc->readFloatRegBits(ArgumentReg[number]);
+            return tc->readFloatRegBits(FirstArgumentReg + number);
         else
-            return tc->readIntReg(ArgumentReg[number]);
+            return tc->readIntReg(FirstArgumentReg + number);
     } else {
         Addr sp = tc->readIntReg(StackPointerReg);
         VirtualPort *vp = tc->getVirtPort();
         uint64_t arg = vp->read<uint64_t>(sp +
-                           (number-NumArgumentRegs) * sizeof(uint64_t));
+                (number - 4) * sizeof(uint64_t));
         return arg;
     }
 #else
@@ -145,7 +148,7 @@ genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
 {
     int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
 
-    fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 |
+    fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
            cc_val << cc_idx |
            bits(fcsr, cc_idx - 1, 0);
 
@@ -233,18 +236,6 @@ isSnan(void *val_ptr, int size)
     }
 }
 
-void
-copyRegs(ThreadContext *src, ThreadContext *dest)
-{
-    panic("Copy Regs Not Implemented Yet\n");
-}
-
-void
-copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-    panic("Copy Misc. Regs Not Implemented Yet\n");
-}
-
 template <class CPU>
 void
 zeroRegisters(CPU *cpu)
@@ -259,7 +250,27 @@ zeroRegisters(CPU *cpu)
 void
 startupCPU(ThreadContext *tc, int cpuId)
 {
-    tc->activate(0/*tc->getThreadNum()*/);
+    tc->activate(0/*tc->threadId()*/);
 }
 
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+    panic("Copy Regs Not Implemented Yet\n");
+}
+
+void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+    panic("Copy Misc. Regs Not Implemented Yet\n");
+}
+void
+skipFunction(ThreadContext *tc)
+{
+    TheISA::PCState newPC = tc->pcState();
+    newPC.set(tc->readIntReg(ReturnAddressReg));
+    tc->pcState(newPC);
+}
+
+
 } // namespace MipsISA