X86: Use IsSquashAfter if an instruction could affect fetch translation.

[gem5.git] / src / arch / mips / utility.cc

diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 8f113fb82227ccf44d9d37fc06f8aeecd6e47fdc..37f71416f8f68131b1d782825fb03ad1f6f83743 100644 (file)
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -28,21 +28,53 @@
  * Authors: Korey Sewell
  */
 
+#include <cmath>
+
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/utility.hh"
-#include "arch/mips/constants.hh"
+#include "base/bitfield.hh"
+#include "base/misc.hh"
 #include "config/full_system.hh"
-#include "cpu/thread_context.hh"
 #include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
 #include "sim/serialize.hh"
-#include "base/bitfield.hh"
-#include "base/misc.hh"
+
+#if FULL_SYSTEM
+#include "arch/mips/registers.hh"
+#include "arch/mips/vtophys.hh"
+#include "mem/vport.hh"
+#endif
+
 
 using namespace MipsISA;
 using namespace std;
 
+namespace MipsISA {
+
+uint64_t
+getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
+{
+#if FULL_SYSTEM
+    if (number < 4) {
+        if (fp)
+            return tc->readFloatRegBits(FirstArgumentReg + number);
+        else
+            return tc->readIntReg(FirstArgumentReg + number);
+    } else {
+        Addr sp = tc->readIntReg(StackPointerReg);
+        VirtualPort *vp = tc->getVirtPort();
+        uint64_t arg = vp->read<uint64_t>(sp +
+                (number - 4) * sizeof(uint64_t));
+        return arg;
+    }
+#else
+    panic("getArgument() is Full system only\n");
+    M5_DUMMY_RETURN
+#endif
+}
+
 uint64_t
-MipsISA::fpConvert(ConvertType cvt_type, double fp_val)
+fpConvert(ConvertType cvt_type, double fp_val)
 {
 
     switch (cvt_type)
@@ -86,7 +118,7 @@ MipsISA::fpConvert(ConvertType cvt_type, double fp_val)
 }
 
 double
-MipsISA::roundFP(double val, int digits)
+roundFP(double val, int digits)
 {
     double digit_offset = pow(10.0,digits);
     val = val * digit_offset;
@@ -97,14 +129,14 @@ MipsISA::roundFP(double val, int digits)
 }
 
 double
-MipsISA::truncFP(double val)
+truncFP(double val)
 {
     int trunc_val = (int) val;
     return (double) trunc_val;
 }
 
 bool
-MipsISA::getCondCode(uint32_t fcsr, int cc_idx)
+getCondCode(uint32_t fcsr, int cc_idx)
 {
     int shift = (cc_idx == 0) ? 23 : cc_idx + 24;
     bool cc_val = (fcsr >> shift) & 0x00000001;
@@ -112,11 +144,11 @@ MipsISA::getCondCode(uint32_t fcsr, int cc_idx)
 }
 
 uint32_t
-MipsISA::genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
+genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
 {
     int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
 
-    fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 |
+    fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
            cc_val << cc_idx |
            bits(fcsr, cc_idx - 1, 0);
 
@@ -124,7 +156,7 @@ MipsISA::genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
 }
 
 uint32_t
-MipsISA::genInvalidVector(uint32_t fcsr_bits)
+genInvalidVector(uint32_t fcsr_bits)
 {
     //Set FCSR invalid in "flag" field
     int invalid_offset = Invalid + Flag_Field;
@@ -138,7 +170,7 @@ MipsISA::genInvalidVector(uint32_t fcsr_bits)
 }
 
 bool
-MipsISA::isNan(void *val_ptr, int size)
+isNan(void *val_ptr, int size)
 {
     switch (size)
     {
@@ -161,7 +193,7 @@ MipsISA::isNan(void *val_ptr, int size)
 
 
 bool
-MipsISA::isQnan(void *val_ptr, int size)
+isQnan(void *val_ptr, int size)
 {
     switch (size)
     {
@@ -183,7 +215,7 @@ MipsISA::isQnan(void *val_ptr, int size)
 }
 
 bool
-MipsISA::isSnan(void *val_ptr, int size)
+isSnan(void *val_ptr, int size)
 {
     switch (size)
     {
@@ -204,8 +236,41 @@ MipsISA::isSnan(void *val_ptr, int size)
     }
 }
 
+template <class CPU>
+void
+zeroRegisters(CPU *cpu)
+{
+    // Insure ISA semantics
+    // (no longer very clean due to the change in setIntReg() in the
+    // cpu model.  Consider changing later.)
+    cpu->thread->setIntReg(ZeroReg, 0);
+    cpu->thread->setFloatReg(ZeroReg, 0.0);
+}
+
+void
+startupCPU(ThreadContext *tc, int cpuId)
+{
+    tc->activate(0/*tc->threadId()*/);
+}
+
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+    panic("Copy Regs Not Implemented Yet\n");
+}
+
+void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+    panic("Copy Misc. Regs Not Implemented Yet\n");
+}
 void
-MipsISA::startupCPU(ThreadContext *tc, int cpuId)
+skipFunction(ThreadContext *tc)
 {
-        tc->activate(0);
+    TheISA::PCState newPC = tc->pcState();
+    newPC.set(tc->readIntReg(ReturnAddressReg));
+    tc->pcState(newPC);
 }
+
+
+} // namespace MipsISA