X86: Use IsSquashAfter if an instruction could affect fetch translation.

[gem5.git] / src / arch / mips / utility.cc

diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index ac90ce45e8ff9d8d3bb4ae7c8ce774fbf29c6f92..37f71416f8f68131b1d782825fb03ad1f6f83743 100644 (file)
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -28,14 +28,16 @@
  * Authors: Korey Sewell
  */
 
+#include <cmath>
+
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/utility.hh"
+#include "base/bitfield.hh"
+#include "base/misc.hh"
 #include "config/full_system.hh"
-#include "cpu/thread_context.hh"
 #include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
 #include "sim/serialize.hh"
-#include "base/bitfield.hh"
-#include "base/misc.hh"
 
 #if FULL_SYSTEM
 #include "arch/mips/registers.hh"
@@ -50,7 +52,7 @@ using namespace std;
 namespace MipsISA {
 
 uint64_t
-getArgument(ThreadContext *tc, int number, bool fp)
+getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
 {
 #if FULL_SYSTEM
     if (number < 4) {
@@ -262,5 +264,13 @@ copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 {
     panic("Copy Misc. Regs Not Implemented Yet\n");
 }
+void
+skipFunction(ThreadContext *tc)
+{
+    TheISA::PCState newPC = tc->pcState();
+    newPC.set(tc->readIntReg(ReturnAddressReg));
+    tc->pcState(newPC);
+}
+
 
 } // namespace MipsISA