/*
- * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
*/
+#include <cmath>
+
#include "arch/mips/isa_traits.hh"
+#include "arch/mips/registers.hh"
#include "arch/mips/utility.hh"
-#include "config/full_system.hh"
+#include "arch/mips/vtophys.hh"
+#include "base/bitfield.hh"
+#include "base/misc.hh"
#include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
+#include "mem/fs_translating_port_proxy.hh"
#include "sim/serialize.hh"
-#include "base/bitfield.hh"
+
using namespace MipsISA;
using namespace std;
+namespace MipsISA {
+
+uint64_t
+getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
+{
+ panic("getArgument() not implemented\n");
+ M5_DUMMY_RETURN
+}
+
uint64_t
-MipsISA::fpConvert(ConvertType cvt_type, double fp_val)
+fpConvert(ConvertType cvt_type, double fp_val)
{
switch (cvt_type)
}
double
-MipsISA::roundFP(double val, int digits)
+roundFP(double val, int digits)
{
double digit_offset = pow(10.0,digits);
val = val * digit_offset;
}
double
-MipsISA::truncFP(double val)
+truncFP(double val)
{
int trunc_val = (int) val;
return (double) trunc_val;
}
bool
-MipsISA::getCondCode(uint32_t fcsr, int cc_idx)
+getCondCode(uint32_t fcsr, int cc_idx)
{
int shift = (cc_idx == 0) ? 23 : cc_idx + 24;
bool cc_val = (fcsr >> shift) & 0x00000001;
}
uint32_t
-MipsISA::genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
+genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
{
int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
- fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 |
+ fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
cc_val << cc_idx |
bits(fcsr, cc_idx - 1, 0);
}
uint32_t
-MipsISA::genInvalidVector(uint32_t fcsr_bits)
+genInvalidVector(uint32_t fcsr_bits)
{
//Set FCSR invalid in "flag" field
int invalid_offset = Invalid + Flag_Field;
}
bool
-MipsISA::isNan(void *val_ptr, int size)
+isNan(void *val_ptr, int size)
{
switch (size)
{
bool
-MipsISA::isQnan(void *val_ptr, int size)
+isQnan(void *val_ptr, int size)
{
switch (size)
{
}
bool
-MipsISA::isSnan(void *val_ptr, int size)
+isSnan(void *val_ptr, int size)
{
switch (size)
{
panic("Type unsupported. Size mismatch\n");
}
}
+
+template <class CPU>
+void
+zeroRegisters(CPU *cpu)
+{
+ // Insure ISA semantics
+ // (no longer very clean due to the change in setIntReg() in the
+ // cpu model. Consider changing later.)
+ cpu->thread->setIntReg(ZeroReg, 0);
+ cpu->thread->setFloatReg(ZeroReg, 0.0);
+}
+
+void
+startupCPU(ThreadContext *tc, int cpuId)
+{
+ tc->activate(0/*tc->threadId()*/);
+}
+
+void
+initCPU(ThreadContext *tc, int cpuId)
+{}
+
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+ panic("Copy Regs Not Implemented Yet\n");
+}
+
+void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+ panic("Copy Misc. Regs Not Implemented Yet\n");
+}
+void
+skipFunction(ThreadContext *tc)
+{
+ TheISA::PCState newPC = tc->pcState();
+ newPC.set(tc->readIntReg(ReturnAddressReg));
+ tc->pcState(newPC);
+}
+
+
+} // namespace MipsISA