sim: Move the BaseTLB to src/arch/generic/

[gem5.git] / src / arch / mips / utility.cc

diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 5908caf68ea7f7a23cd915b492ff0f0e919ef855..80047fbfdca3b439f2ca14822d867dcca126d664 100644 (file)
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -28,19 +28,18 @@
  * Authors: Korey Sewell
  */
 
+#include <cmath>
+
 #include "arch/mips/isa_traits.hh"
+#include "arch/mips/registers.hh"
 #include "arch/mips/utility.hh"
-#include "config/full_system.hh"
-#include "cpu/thread_context.hh"
-#include "cpu/static_inst.hh"
-#include "sim/serialize.hh"
+#include "arch/mips/vtophys.hh"
 #include "base/bitfield.hh"
 #include "base/misc.hh"
-
-#if FULL_SYSTEM
-#include "arch/mips/vtophys.hh"
-#include "mem/vport.hh"
-#endif
+#include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
+#include "mem/fs_translating_port_proxy.hh"
+#include "sim/serialize.hh"
 
 
 using namespace MipsISA;
@@ -49,25 +48,10 @@ using namespace std;
 namespace MipsISA {
 
 uint64_t
-getArgument(ThreadContext *tc, int number, bool fp)
+getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
 {
-#if FULL_SYSTEM
-    if (number < NumArgumentRegs) {
-        if (fp)
-            return tc->readFloatRegBits(ArgumentReg[number]);
-        else
-            return tc->readIntReg(ArgumentReg[number]);
-    } else {
-        Addr sp = tc->readIntReg(StackPointerReg);
-        VirtualPort *vp = tc->getVirtPort();
-        uint64_t arg = vp->read<uint64_t>(sp +
-                           (number-NumArgumentRegs) * sizeof(uint64_t));
-        return arg;
-    }
-#else
-    panic("getArgument() is Full system only\n");
+    panic("getArgument() not implemented\n");
     M5_DUMMY_RETURN
-#endif
 }
 
 uint64_t
@@ -233,18 +217,6 @@ isSnan(void *val_ptr, int size)
     }
 }
 
-void
-copyRegs(ThreadContext *src, ThreadContext *dest)
-{
-    panic("Copy Regs Not Implemented Yet\n");
-}
-
-void
-copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-    panic("Copy Misc. Regs Not Implemented Yet\n");
-}
-
 template <class CPU>
 void
 zeroRegisters(CPU *cpu)
@@ -259,7 +231,47 @@ zeroRegisters(CPU *cpu)
 void
 startupCPU(ThreadContext *tc, int cpuId)
 {
-    tc->activate(0/*tc->threadId()*/);
+    tc->activate();
 }
 
+void
+initCPU(ThreadContext *tc, int cpuId)
+{}
+
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+    // First loop through the integer registers.
+    for (int i = 0; i < NumIntRegs; i++)
+        dest->setIntRegFlat(i, src->readIntRegFlat(i));
+
+    // Then loop through the floating point registers.
+    for (int i = 0; i < NumFloatRegs; i++)
+        dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
+
+    // Would need to add condition-code regs if implemented
+    assert(NumCCRegs == 0);
+
+    // Copy misc. registers
+    for (int i = 0; i < NumMiscRegs; i++)
+        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
+
+    // Copy over the PC State
+    dest->pcState(src->pcState());
+}
+
+void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+    panic("Copy Misc. Regs Not Implemented Yet\n");
+}
+void
+skipFunction(ThreadContext *tc)
+{
+    TheISA::PCState newPC = tc->pcState();
+    newPC.set(tc->readIntReg(ReturnAddressReg));
+    tc->pcState(newPC);
+}
+
+
 } // namespace MipsISA