sim: Move the BaseTLB to src/arch/generic/

[gem5.git] / src / arch / mips / utility.cc

diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index e7455fdbf4df940a952c893c1e7c93537840f491..80047fbfdca3b439f2ca14822d867dcca126d664 100644 (file)
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -28,18 +28,34 @@
  * Authors: Korey Sewell
  */
 
+#include <cmath>
+
 #include "arch/mips/isa_traits.hh"
+#include "arch/mips/registers.hh"
 #include "arch/mips/utility.hh"
-#include "config/full_system.hh"
+#include "arch/mips/vtophys.hh"
+#include "base/bitfield.hh"
+#include "base/misc.hh"
 #include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
+#include "mem/fs_translating_port_proxy.hh"
 #include "sim/serialize.hh"
-#include "base/bitfield.hh"
+
 
 using namespace MipsISA;
 using namespace std;
 
+namespace MipsISA {
+
 uint64_t
-MipsISA::fpConvert(ConvertType cvt_type, double fp_val)
+getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
+{
+    panic("getArgument() not implemented\n");
+    M5_DUMMY_RETURN
+}
+
+uint64_t
+fpConvert(ConvertType cvt_type, double fp_val)
 {
 
     switch (cvt_type)
@@ -83,7 +99,7 @@ MipsISA::fpConvert(ConvertType cvt_type, double fp_val)
 }
 
 double
-MipsISA::roundFP(double val, int digits)
+roundFP(double val, int digits)
 {
     double digit_offset = pow(10.0,digits);
     val = val * digit_offset;
@@ -94,14 +110,14 @@ MipsISA::roundFP(double val, int digits)
 }
 
 double
-MipsISA::truncFP(double val)
+truncFP(double val)
 {
     int trunc_val = (int) val;
     return (double) trunc_val;
 }
 
 bool
-MipsISA::getCondCode(uint32_t fcsr, int cc_idx)
+getCondCode(uint32_t fcsr, int cc_idx)
 {
     int shift = (cc_idx == 0) ? 23 : cc_idx + 24;
     bool cc_val = (fcsr >> shift) & 0x00000001;
@@ -109,11 +125,11 @@ MipsISA::getCondCode(uint32_t fcsr, int cc_idx)
 }
 
 uint32_t
-MipsISA::genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
+genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
 {
     int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
 
-    fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 |
+    fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
            cc_val << cc_idx |
            bits(fcsr, cc_idx - 1, 0);
 
@@ -121,7 +137,7 @@ MipsISA::genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
 }
 
 uint32_t
-MipsISA::genInvalidVector(uint32_t fcsr_bits)
+genInvalidVector(uint32_t fcsr_bits)
 {
     //Set FCSR invalid in "flag" field
     int invalid_offset = Invalid + Flag_Field;
@@ -135,7 +151,7 @@ MipsISA::genInvalidVector(uint32_t fcsr_bits)
 }
 
 bool
-MipsISA::isNan(void *val_ptr, int size)
+isNan(void *val_ptr, int size)
 {
     switch (size)
     {
@@ -158,7 +174,7 @@ MipsISA::isNan(void *val_ptr, int size)
 
 
 bool
-MipsISA::isQnan(void *val_ptr, int size)
+isQnan(void *val_ptr, int size)
 {
     switch (size)
     {
@@ -180,7 +196,7 @@ MipsISA::isQnan(void *val_ptr, int size)
 }
 
 bool
-MipsISA::isSnan(void *val_ptr, int size)
+isSnan(void *val_ptr, int size)
 {
     switch (size)
     {
@@ -200,3 +216,62 @@ MipsISA::isSnan(void *val_ptr, int size)
         panic("Type unsupported. Size mismatch\n");
     }
 }
+
+template <class CPU>
+void
+zeroRegisters(CPU *cpu)
+{
+    // Insure ISA semantics
+    // (no longer very clean due to the change in setIntReg() in the
+    // cpu model.  Consider changing later.)
+    cpu->thread->setIntReg(ZeroReg, 0);
+    cpu->thread->setFloatReg(ZeroReg, 0.0);
+}
+
+void
+startupCPU(ThreadContext *tc, int cpuId)
+{
+    tc->activate();
+}
+
+void
+initCPU(ThreadContext *tc, int cpuId)
+{}
+
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+    // First loop through the integer registers.
+    for (int i = 0; i < NumIntRegs; i++)
+        dest->setIntRegFlat(i, src->readIntRegFlat(i));
+
+    // Then loop through the floating point registers.
+    for (int i = 0; i < NumFloatRegs; i++)
+        dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
+
+    // Would need to add condition-code regs if implemented
+    assert(NumCCRegs == 0);
+
+    // Copy misc. registers
+    for (int i = 0; i < NumMiscRegs; i++)
+        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
+
+    // Copy over the PC State
+    dest->pcState(src->pcState());
+}
+
+void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+    panic("Copy Misc. Regs Not Implemented Yet\n");
+}
+void
+skipFunction(ThreadContext *tc)
+{
+    TheISA::PCState newPC = tc->pcState();
+    newPC.set(tc->readIntReg(ReturnAddressReg));
+    tc->pcState(newPC);
+}
+
+
+} // namespace MipsISA