sim: Move the BaseTLB to src/arch/generic/

[gem5.git] / src / arch / mips / utility.cc

diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index ff410bad11a876191dba16ec99adc19405ff432a..80047fbfdca3b439f2ca14822d867dcca126d664 100644 (file)
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -231,7 +231,7 @@ zeroRegisters(CPU *cpu)
 void
 startupCPU(ThreadContext *tc, int cpuId)
 {
-    tc->activate(Cycles(0));
+    tc->activate();
 }
 
 void