#ifndef __ARCH_MIPS_UTILITY_HH__
#define __ARCH_MIPS_UTILITY_HH__
-#include "config/full_system.hh"
-#include "arch/mips/types.hh"
#include "arch/mips/isa_traits.hh"
+#include "arch/mips/types.hh"
#include "base/misc.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
+#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
class ThreadContext;
namespace MipsISA {
-uint64_t getArgument(ThreadContext *tc, int number, bool fp);
+inline PCState
+buildRetPC(const PCState &curPC, const PCState &callPC)
+{
+ PCState ret = callPC;
+ ret.advance();
+ ret.pc(curPC.npc());
+ return ret;
+}
+
+uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
////////////////////////////////////////////////////////////////////////
//
static inline bool
inUserMode(ThreadContext *tc)
{
- MiscReg Stat = tc->readMiscReg(MipsISA::Status);
- MiscReg Dbg = tc->readMiscReg(MipsISA::Debug);
+ MiscReg Stat = tc->readMiscReg(MISCREG_STATUS);
+ MiscReg Dbg = tc->readMiscReg(MISCREG_DEBUG);
if ((Stat & 0x10000006) == 0 && // EXL, ERL or CU0 set, CP0 accessible
(Dbg & 0x40000000) == 0 && // DM bit set, CP0 accessible
}
}
-// Instruction address compression hooks
-static inline Addr realPCToFetchPC(const Addr &addr) {
- return addr;
-}
-
-static inline Addr fetchPCToRealPC(const Addr &addr) {
- return addr;
-}
-
-// the size of "fetched" instructions (not necessarily the size
-// of real instructions for PISA)
-static inline size_t fetchInstSize() {
- return sizeof(MachInst);
-}
-
-////////////////////////////////////////////////////////////////////////
-//
-// Register File Utility Functions
-//
-static inline MachInst makeRegisterCopy(int dest, int src) {
- panic("makeRegisterCopy not implemented");
- return 0;
-}
-
template <class CPU>
void zeroRegisters(CPU *cpu);
// CPU Utility
//
void startupCPU(ThreadContext *tc, int cpuId);
+void initCPU(ThreadContext *tc, int cpuId);
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+void skipFunction(ThreadContext *tc);
+
+inline void
+advancePC(PCState &pc, const StaticInstPtr inst)
+{
+ pc.advance();
+}
+
+inline uint64_t
+getExecutingAsid(ThreadContext *tc)
+{
+ return 0;
+}
+
};