cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.

[gem5.git] / src / arch / mips / utility.hh

diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 37cd838e5d51859269e317fa0a1411981625d4b5..87606620355b1c312dcc68957a4fc50dc72e47d6 100644 (file)
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -33,19 +33,27 @@
 
 #ifndef __ARCH_MIPS_UTILITY_HH__
 #define __ARCH_MIPS_UTILITY_HH__
-#include "config/full_system.hh"
-#include "arch/mips/types.hh"
 #include "arch/mips/isa_traits.hh"
+#include "arch/mips/types.hh"
 #include "base/misc.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
+#include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 
 class ThreadContext;
 
 namespace MipsISA {
 
-uint64_t getArgument(ThreadContext *tc, int number, bool fp);
+inline PCState
+buildRetPC(const PCState &curPC, const PCState &callPC)
+{
+    PCState ret = callPC;
+    ret.advance();
+    ret.pc(curPC.npc());
+    return ret;
+}
+
+uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
 
 ////////////////////////////////////////////////////////////////////////
 //
@@ -66,8 +74,8 @@ bool isSnan(void *val_ptr, int size);
 static inline bool
 inUserMode(ThreadContext *tc)
 {
-    MiscReg Stat = tc->readMiscReg(MipsISA::Status);
-    MiscReg Dbg = tc->readMiscReg(MipsISA::Debug);
+    MiscReg Stat = tc->readMiscReg(MISCREG_STATUS);
+    MiscReg Dbg = tc->readMiscReg(MISCREG_DEBUG);
 
     if ((Stat & 0x10000006) == 0 &&  // EXL, ERL or CU0 set, CP0 accessible
         (Dbg & 0x40000000) == 0 &&   // DM bit set, CP0 accessible
@@ -79,30 +87,6 @@ inUserMode(ThreadContext *tc)
     }
 }
 
-// Instruction address compression hooks
-static inline Addr realPCToFetchPC(const Addr &addr) {
-    return addr;
-}
-
-static inline Addr fetchPCToRealPC(const Addr &addr) {
-    return addr;
-}
-
-// the size of "fetched" instructions (not necessarily the size
-// of real instructions for PISA)
-static inline size_t fetchInstSize() {
-    return sizeof(MachInst);
-}
-
-////////////////////////////////////////////////////////////////////////
-//
-//  Register File Utility Functions
-//
-static inline MachInst makeRegisterCopy(int dest, int src) {
-    panic("makeRegisterCopy not implemented");
-    return 0;
-}
-
 template <class CPU>
 void zeroRegisters(CPU *cpu);
 
@@ -123,10 +107,25 @@ RoundPage(Addr addr)
 // CPU Utility
 //
 void startupCPU(ThreadContext *tc, int cpuId);
+void initCPU(ThreadContext *tc, int cpuId);
 
 void copyRegs(ThreadContext *src, ThreadContext *dest);
 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 
+void skipFunction(ThreadContext *tc);
+
+inline void
+advancePC(PCState &pc, const StaticInstPtr inst)
+{
+    pc.advance();
+}
+
+inline uint64_t
+getExecutingAsid(ThreadContext *tc)
+{
+    return 0;
+}
+
 };