cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.

[gem5.git] / src / arch / mips / utility.hh

diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 6195c4ceb594d7828a6359ce9fec417184d84e97..87606620355b1c312dcc68957a4fc50dc72e47d6 100644 (file)
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -33,81 +33,99 @@
 
 #ifndef __ARCH_MIPS_UTILITY_HH__
 #define __ARCH_MIPS_UTILITY_HH__
-
-#include "arch/mips/types.hh"
 #include "arch/mips/isa_traits.hh"
+#include "arch/mips/types.hh"
 #include "base/misc.hh"
-#include "config/full_system.hh"
-//XXX This is needed for size_t. We should use something other than size_t
-//#include "kern/linux/linux.hh"
-#include "sim/host.hh"
-
+#include "base/types.hh"
+#include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 
 class ThreadContext;
 
 namespace MipsISA {
 
-    uint64_t getArgument(ThreadContext *tc, bool fp) {
-        panic("getArgument() not implemented for MIPS\n");
-    }
-
-    //Floating Point Utility Functions
-    uint64_t fpConvert(ConvertType cvt_type, double fp_val);
-    double roundFP(double val, int digits);
-    double truncFP(double val);
-
-    bool getCondCode(uint32_t fcsr, int cc);
-    uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val);
-    uint32_t genInvalidVector(uint32_t fcsr);
-
-    bool isNan(void *val_ptr, int size);
-    bool isQnan(void *val_ptr, int size);
-    bool isSnan(void *val_ptr, int size);
-
-    /**
-     * Function to insure ISA semantics about 0 registers.
-     * @param tc The thread context.
-     */
-    template <class TC>
-    void zeroRegisters(TC *tc);
-
-    void startupCPU(ThreadContext *tc, int cpuId);
-
-    void copyRegs(ThreadContext *src, ThreadContext *dest);
-
-    // Instruction address compression hooks
-    static inline Addr realPCToFetchPC(const Addr &addr) {
-        return addr;
-    }
-
-    static inline Addr fetchPCToRealPC(const Addr &addr) {
-        return addr;
-    }
-
-    // the size of "fetched" instructions (not necessarily the size
-    // of real instructions for PISA)
-    static inline size_t fetchInstSize() {
-        return sizeof(MachInst);
-    }
-
-    static inline MachInst makeRegisterCopy(int dest, int src) {
-        panic("makeRegisterCopy not implemented");
-        return 0;
+inline PCState
+buildRetPC(const PCState &curPC, const PCState &callPC)
+{
+    PCState ret = callPC;
+    ret.advance();
+    ret.pc(curPC.npc());
+    return ret;
+}
+
+uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
+
+////////////////////////////////////////////////////////////////////////
+//
+// Floating Point Utility Functions
+//
+uint64_t fpConvert(ConvertType cvt_type, double fp_val);
+double roundFP(double val, int digits);
+double truncFP(double val);
+
+bool getCondCode(uint32_t fcsr, int cc);
+uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val);
+uint32_t genInvalidVector(uint32_t fcsr);
+
+bool isNan(void *val_ptr, int size);
+bool isQnan(void *val_ptr, int size);
+bool isSnan(void *val_ptr, int size);
+
+static inline bool
+inUserMode(ThreadContext *tc)
+{
+    MiscReg Stat = tc->readMiscReg(MISCREG_STATUS);
+    MiscReg Dbg = tc->readMiscReg(MISCREG_DEBUG);
+
+    if ((Stat & 0x10000006) == 0 &&  // EXL, ERL or CU0 set, CP0 accessible
+        (Dbg & 0x40000000) == 0 &&   // DM bit set, CP0 accessible
+        (Stat & 0x00000018) != 0) {  // KSU = 0, kernel mode is base mode
+        // Unable to use Status_CU0, etc directly, using bitfields & masks
+        return true;
+    } else {
+        return false;
     }
+}
+
+template <class CPU>
+void zeroRegisters(CPU *cpu);
+
+////////////////////////////////////////////////////////////////////////
+//
+//  Translation stuff
+//
+inline Addr
+TruncPage(Addr addr)
+{ return addr & ~(PageBytes - 1); }
+
+inline Addr
+RoundPage(Addr addr)
+{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
+
+////////////////////////////////////////////////////////////////////////
+//
+// CPU Utility
+//
+void startupCPU(ThreadContext *tc, int cpuId);
+void initCPU(ThreadContext *tc, int cpuId);
+
+void copyRegs(ThreadContext *src, ThreadContext *dest);
+void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
+void skipFunction(ThreadContext *tc);
+
+inline void
+advancePC(PCState &pc, const StaticInstPtr inst)
+{
+    pc.advance();
+}
+
+inline uint64_t
+getExecutingAsid(ThreadContext *tc)
+{
+    return 0;
+}
 
-    static inline ExtMachInst
-    makeExtMI(MachInst inst, ThreadContext * xc) {
-#if FULL_SYSTEM
-        ExtMachInst ext_inst = inst;
-        if (xc->readPC() && 0x1)
-            return ext_inst|=(static_cast<ExtMachInst>(xc->readPC() & 0x1) << 32);
-        else
-            return ext_inst;
-#else
-        return ExtMachInst(inst);
-#endif
-    }
 };