/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Authors: Nathan Binkert
* Steve Reinhardt
+ * Korey Sewell
*/
#ifndef __ARCH_MIPS_UTILITY_HH__
#define __ARCH_MIPS_UTILITY_HH__
-
+#include "arch/mips/isa_traits.hh"
#include "arch/mips/types.hh"
-#include "arch/mips/constants.hh"
#include "base/misc.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
+#include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
+
+class ThreadContext;
namespace MipsISA {
- //Floating Point Utility Functions
- uint64_t fpConvert(ConvertType cvt_type, double fp_val);
- double roundFP(double val, int digits);
- double truncFP(double val);
+inline PCState
+buildRetPC(const PCState &curPC, const PCState &callPC)
+{
+ PCState ret = callPC;
+ ret.advance();
+ ret.pc(curPC.npc());
+ return ret;
+}
+
+uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
+
+////////////////////////////////////////////////////////////////////////
+//
+// Floating Point Utility Functions
+//
+uint64_t fpConvert(ConvertType cvt_type, double fp_val);
+double roundFP(double val, int digits);
+double truncFP(double val);
+
+bool getCondCode(uint32_t fcsr, int cc);
+uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val);
+uint32_t genInvalidVector(uint32_t fcsr);
+
+bool isNan(void *val_ptr, int size);
+bool isQnan(void *val_ptr, int size);
+bool isSnan(void *val_ptr, int size);
+
+static inline bool
+inUserMode(ThreadContext *tc)
+{
+ MiscReg Stat = tc->readMiscReg(MISCREG_STATUS);
+ MiscReg Dbg = tc->readMiscReg(MISCREG_DEBUG);
+
+ if ((Stat & 0x10000006) == 0 && // EXL, ERL or CU0 set, CP0 accessible
+ (Dbg & 0x40000000) == 0 && // DM bit set, CP0 accessible
+ (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
+ // Unable to use Status_CU0, etc directly, using bitfields & masks
+ return true;
+ } else {
+ return false;
+ }
+}
+
+template <class CPU>
+void zeroRegisters(CPU *cpu);
+
+////////////////////////////////////////////////////////////////////////
+//
+// Translation stuff
+//
+inline Addr
+TruncPage(Addr addr)
+{ return addr & ~(PageBytes - 1); }
+
+inline Addr
+RoundPage(Addr addr)
+{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
+
+////////////////////////////////////////////////////////////////////////
+//
+// CPU Utility
+//
+void startupCPU(ThreadContext *tc, int cpuId);
+void initCPU(ThreadContext *tc, int cpuId);
+
+void copyRegs(ThreadContext *src, ThreadContext *dest);
+void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
+void skipFunction(ThreadContext *tc);
+
+inline void
+advancePC(PCState &pc, const StaticInstPtr inst)
+{
+ pc.advance();
+}
- bool getCondCode(uint32_t fcsr, int cc);
- uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val);
- uint32_t genInvalidVector(uint32_t fcsr);
+inline uint64_t
+getExecutingAsid(ThreadContext *tc)
+{
+ return 0;
+}
- bool isNan(void *val_ptr, int size);
- bool isQnan(void *val_ptr, int size);
- bool isSnan(void *val_ptr, int size);
};