sim: Move the BaseTLB to src/arch/generic/

[gem5.git] / src / arch / mips / vtophys.cc

diff --git a/src/arch/mips/vtophys.cc b/src/arch/mips/vtophys.cc
index c6a317df893162c16ef7b6c2738530be6a14b8cc..60d9bc1baea14188f7c123acb63f346cdad4c9f4 100755 (executable)
--- a/src/arch/mips/vtophys.cc
+++ b/src/arch/mips/vtophys.cc
@@ -38,7 +38,6 @@
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
 #include "debug/VtoPhys.hh"
-#include "mem/vport.hh"
 
 using namespace std;
 using namespace MipsISA;