sim: Move the BaseTLB to src/arch/generic/

[gem5.git] / src / arch / mips / vtophys.cc

diff --git a/src/arch/mips/vtophys.cc b/src/arch/mips/vtophys.cc
index dc212862bf7c8d9a2f08658305cdaa042444a366..60d9bc1baea14188f7c123acb63f346cdad4c9f4 100755 (executable)
--- a/src/arch/mips/vtophys.cc
+++ b/src/arch/mips/vtophys.cc
@@ -37,7 +37,7 @@
 #include "base/chunk_generator.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
-#include "mem/vport.hh"
+#include "debug/VtoPhys.hh"
 
 using namespace std;
 using namespace MipsISA;
@@ -45,25 +45,13 @@ using namespace MipsISA;
 Addr
 MipsISA::vtophys(Addr vaddr)
 {
-    Addr paddr = 0;
-    if (MipsISA::IsUSeg(vaddr))
-        DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
-    else if (MipsISA::IsKSeg0(vaddr))
-        paddr = MipsISA::KSeg02Phys(vaddr);
-    else if(MipsISA::IsKSeg1(vaddr))
-        paddr = MipsISA::KSeg12Phys(vaddr);
-    else
-        panic("vtophys: ptbr is not set on virtual lookup for vaddr %#x", vaddr);
-
-    DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
-
-    return paddr;
+    fatal("VTOPHYS: Unimplemented on MIPS\n");
+    return 0;
 }
 
 Addr
 MipsISA::vtophys(ThreadContext *tc, Addr addr)
 {
-
-  fatal("VTOPHYS: Unimplemented on MIPS\n");
+    fatal("VTOPHYS: Unimplemented on MIPS\n");
 }