cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.

[gem5.git] / src / arch / mips / vtophys.hh

diff --git a/src/arch/mips/vtophys.hh b/src/arch/mips/vtophys.hh
index 741ac36bc49deb2abbd6fc5faa57f113584b30cd..a3fbdd457a5191d635b55eaf6a7f6fd8bf460fbe 100644 (file)
--- a/src/arch/mips/vtophys.hh
+++ b/src/arch/mips/vtophys.hh
@@ -40,24 +40,6 @@
 class ThreadContext;
 
 namespace MipsISA {
-    inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
-
-    // User Virtual
-    inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
-
-    inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; }
-
-    inline Addr KSeg02Phys(Addr addr) { return addr & KSeg0Mask; }
-
-    inline Addr KSeg12Phys(Addr addr) { return addr & KSeg1Mask; }
-
-    inline bool IsKSeg1(Addr a) { return KSeg1Base <= a && a <= KSeg1End; }
-
-    inline bool IsKSSeg(Addr a) { return KSSegBase <= a && a <= KSSegEnd; }
-
-    inline bool IsKSeg3(Addr a) { return KSeg3Base <= a && a <= KSeg3End; }
-
-
     Addr vtophys(Addr vaddr);
     Addr vtophys(ThreadContext *tc, Addr vaddr);