MSR = insertBits(MSR,11,6,bits(SRR1,11,6));
MSR = insertBits(MSR,3,0,bits(SRR1,3,0));
NIA = SRR0 & -4ULL;
- }});
+ }}, [ IsPrivileged ]);
274: hrfid({{
if((bits(MSR,34,32)!=0x02)|(bits(HSRR1,34,32)!=0x00))
MSR = insertBits(MSR,34,32,bits(HSRR1,34,32));
}
}
- 17: IntOp::sc({{ xc->syscall(R0, &fault); }},
- [ IsSyscall, IsNonSpeculative, IsSerializeAfter ]);
+//TODO:Right now sc instruction not handles LEV=1 case
+
+ format IntOp {
+ 17: sc({{
+ if (FullSystem) {
+ fault= std::make_shared<SystemCallInterrupt>();
+ } else {
+ xc->syscall(R0, &fault);
+ }
+ }},
+ [ IsSyscall, IsNonSpeculative, IsSerializeAfter ]);
+ }
format LoadDispOp {
34: lbz({{ Rt = Mem_ub; }});
format StoreDispOp {
38: stb({{ Mem_ub = Rs_ub; }});
44: sth({{ Mem_uh = Rs_uh; }});
- 36: stw({{ Mem = Rs_uw; }});
+ 36: stw({{ Mem_uw = Rs_uw; }});
}
format StoreDispUpdateOp {
39: stbu({{ Mem_ub = Rs_ub; }});
45: sthu({{ Mem_uh = Rs_uh; }});
- 37: stwu({{ Mem = Rs_uw; }});
+ 37: stwu({{ Mem_uw = Rs_uw; }});
}
format IntImmArithCheckRaOp {
}
}
+
+ format IntImmArithOp {
+
+ 3: twi({{
+ if(FullSystem) {
+ int32_t val = Ra_sw;
+ if(((TO & 0x10) && (val < simm)) ||
+ ((TO & 0x08) && (val > simm)) ||
+ ((TO & 0x04) && (val == simm)) ||
+ ((TO & 0x02) && ((uint32_t)val < (uint32_t)simm)) ||
+ ((TO & 0x01) && ((uint32_t)val > (uint32_t)simm))) {
+ fault= std::make_shared<ProgramTrapInterrupt>();
+ }
+ }
+ }});
+
+ 2: tdi({{
+ if(FullSystem) {
+ int64_t val1 = Ra_sd;
+ int64_t val2 = simm;
+ //printf("Val 1 : 0x%016lx val2: 0x%016lx\n", val,val2);
+ if(((TO & 0x10) && (val1 < val2)) ||
+ ((TO & 0x08) && (val1 > val2)) ||
+ ((TO & 0x04) && (val1 == val2)) ||
+ ((TO & 0x02) && ((uint64_t)val1 < (uint64_t)val2)) ||
+ ((TO & 0x01) && ((uint64_t)val1 > (uint64_t)val2))) {
+ fault= std::make_shared<ProgramTrapInterrupt>();
+ }
+ }
+ }});
+ }
+
format IntImmCompOp {
11: cmpi({{
if (length) {
// Ra and Rb are source registers, Rt is the destintation.
format LoadIndexOp {
87: lbzx({{ Rt = Mem_ub; }});
- 52: lbarx({{ Rt = Mem_ub; Rsv = 1; RsvLen = 1; RsvAddr = EA; }});
+ 52: lbarx({{ Rt = Mem_ub; }}, mem_flags = LLSC);
279: lhzx({{ Rt = Mem_uh; }});
343: lhax({{ Rt = Mem_sh; }});
- 116: lharx({{ Rt = Mem_uh; Rsv = 1; RsvLen = 2; RsvAddr = EA; }});
+ 116: lharx({{ Rt = Mem_uh; }}, mem_flags = LLSC);
790: lhbrx({{ Rt = swap_byte(Mem_uh); }});
23: lwzx({{ Rt = Mem_uw; }});
341: lwax({{ Rt = Mem_sw; }});
- 20: lwarx({{ Rt = Mem_uw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
+ 20: lwarx({{ Rt = Mem_uw; }}, mem_flags = LLSC);
534: lwbrx({{ Rt = swap_byte(Mem_uw); }});
21: ldx({{ Rt = Mem; }});
- 84: ldarx({{ Rt = Mem_ud; Rsv = 1; RsvLen = 8; RsvAddr = EA; }});
+ 84: ldarx({{ Rt = Mem_ud; }}, mem_flags = LLSC);
532: ldbrx({{ Rt = swap_byte(Mem); }});
535: lfsx({{ Ft_sf = Mem_sf; }});
599: lfdx({{ Ft = Mem_df; }});
format StoreIndexOp {
215: stbx({{ Mem_ub = Rs_ub; }});
- 694: stbcx({{
- bool store_performed = false;
- Mem_ub = Rs_ub;
- if (Rsv) {
- if (RsvLen == 1) {
- if (RsvAddr == EA) {
- store_performed = true;
- }
- }
- }
- Xer xer = XER;
- Cr cr = CR;
- cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
- CR = cr;
- Rsv = 0;
- }});
+ 694: stbcx({{ Mem_ub = Rs_ub; }}, mem_flags = LLSC);
407: sthx({{ Mem_uh = Rs_uh; }});
- 726: sthcx({{
- bool store_performed = false;
- Mem_uh = Rs_uh;
- if (Rsv) {
- if (RsvLen == 2) {
- if (RsvAddr == EA) {
- store_performed = true;
- }
- }
- }
- Xer xer = XER;
- Cr cr = CR;
- cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
- CR = cr;
- Rsv = 0;
- }});
+ 726: sthcx({{ Mem_uh = Rs_uh; }}, mem_flags = LLSC);
918: sthbrx({{ Mem_uh = swap_byte(Rs_uh); }});
151: stwx({{ Mem_uw = Rs_uw; }});
- 150: stwcx({{
- bool store_performed = false;
- Mem_uw = Rs_uw;
- if (Rsv) {
- if (RsvLen == 4) {
- if (RsvAddr == EA) {
- store_performed = true;
- }
- }
- }
- Xer xer = XER;
- Cr cr = CR;
- cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
- CR = cr;
- Rsv = 0;
- }});
+ 150: stwcx({{ Mem_uw = Rs_uw; }}, mem_flags = LLSC);
662: stwbrx({{ Mem_uw = swap_byte(Rs_uw); }});
149: stdx({{ Mem = Rs }});
- 214: stdcx({{
- bool store_performed = false;
- Mem = Rs;
- if (Rsv) {
- if (RsvLen == 8) {
- if (RsvAddr == EA) {
- store_performed = true;
- }
- }
- }
- Xer xer = XER;
- Cr cr = CR;
- cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
- CR = cr;
- Rsv = 0;
- }});
+ 214: stdcx({{ Mem_ud = Rs; }}, mem_flags = LLSC);
660: stdbrx({{ Mem = swap_byte(Rs); }});
}
}
format IntArithOp {
- 779: modsw({{
+
+ 4: tw({{
+ if(FullSystem) {
+ int32_t val1 = Ra_sw;
+ int32_t val2 = Rb_sw;
+ if(((TO & 0x10) && (val1 < val2)) ||
+ ((TO & 0x08) && (val1 > val2)) ||
+ ((TO & 0x04) && (val1 == val2)) ||
+ ((TO & 0x02) && ((uint32_t)val1 < (uint32_t)val2)) ||
+ ((TO & 0x01) && ((uint32_t)val1 > (uint32_t)val2))) {
+ fault= std::make_shared<ProgramTrapInterrupt>();
+ }
+ }
+
+ }});
+
+ 68: td ({{
+ if(FullSystem) {
+ int64_t val1 = Ra_sd;
+ int64_t val2 = Rb_sd;
+ if(((TO & 0x10) && (val1 < val2)) ||
+ ((TO & 0x08) && (val1 > val2)) ||
+ ((TO & 0x04) && (val1 == val2)) ||
+ ((TO & 0x02) && ((uint64_t)val1 < (uint64_t)val2)) ||
+ ((TO & 0x01) && ((uint64_t)val1 > (uint64_t)val2))) {
+ fault= std::make_shared<ProgramTrapInterrupt>();
+ }
+ }
+ }});
+
+ 779: modsw({{
int64_t src1 = Ra_sw;
int64_t src2 = Rb_sw;
if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {
}
}});
+ //TODO: Right now we doesn't support DARN instruction
+ // Not returning random number, Just Setting value to -1.
+ //Need to FIX that instruction
+
+ 755: darn({{
+ Rt = -1;
+ }});
+
777: modsd({{
int64_t src1 = Ra_sd;
int64_t src2 = Rb_sd;
// Generic integer format instructions.
format IntOp {
339: decode SPR {
- 0x20: mfxer({{ Rt = XER; }});
+ 0x004: mftfhar({{ Rt = TFHAR; }});
+ 0x008: mfvrsave({{ Rt = VRSAVE; }});
+ 0x018: mfsier({{Rt = SIER;}});
+ 0x019: mfbescrs({{Rt = BESCRS;}});
+ 0x01C: mfppr({{ Rt = PPR; }});
+ 0x020: mfxer({{ Rt = XER; }});
+ 0x024: mftfiar({{ Rt = TFIAR; }});
+ 0x039: mfbescrsu({{Rt = BESCRSU;}});
+ 0x044: mftexasr({{ Rt = TEXASR; }});
+ 0x05C: mfppr2({{ Rt =PPR32; }});
+ 0x078: mfupmc1({{Rt = PMC1;}});
+ 0x098: mfupmc2({{Rt = PMC2;}});
+ 0x099: mfebbhr({{Rt = EBBHR;}});
+ 0x0b8: mfupmc3({{Rt = PMC3;}});
+ 0x0b9: mfebbrr({{Rt = EBBRR;}});
+ 0x0d8: mfupmc4({{Rt = PMC4;}});
+ 0x0d9: mfbescr({{Rt = BESCR;}});
+ 0x0f8: mfupmc5({{Rt = PMC5;}});
0x100: mflr({{ Rt = LR; }});
+ 0x104: mfctrl({{ Rt = CTRL; }});
+ 0x118: mfupmc6r({{Rt = PMC6;}});
0x120: mfctr({{ Rt = CTR; }});
0x188: mftb({{ Rt = TB; }});
+ 0x1A8: mftbu({{ Rt = TBU; }});
+ 0x1b8: mfsdar({{Rt = SDAR;}});
+ 0x1f9: mftar({{Rt = TAR;}});
+ 0x204: mftidr({{ Rt = TIDR; }}, [ IsPrivileged ]);
+ 0x205: mfdpdes({{ Rt = DPDES; }}, [ IsPrivileged ]);
+ 0x208: mfsprg0({{Rt = SPRG0;}});
+ 0x209: mfhsprg0({{Rt = HSPRG0;}});
+ 0x20a: mfhmer({{Rt = HMER;}});
+ 0x20E: mfptcr({{ Rt = PTCR; }});
+ 0x219: mfasdr({{Rt = ASDR;}});
+ 0x21a: mfic({{Rt = IC;}}, [ IsPrivileged ]);
+ 0x21f: mfhir0({{Rt = HIR0;}});
0x220: mfdscr({{ Rt = DSCR; }});
+ 0x228: mfsprg1({{Rt = SPRG1;}});
+ 0x229: mfhsprg1({{Rt = HSPRG1;}});
+ 0x22a: mfhmeer({{Rt = HMEER;}});
+ 0x23a: mfvtb({{Rt = VTB;}}, [ IsPrivileged ]);
0x240: mfdsisr({{ Rt = DSISR; }});
+ 0x248: mfsprg2({{Rt = SPRG2;}});
+ 0x249: mfhdisr({{Rt = HDSISR;}});
+ 0x24a: mfpcr({{Rt = PCR;}});
0x260: mfdar({{ Rt = DAR; }});
+ 0x268: mfsprg3({{Rt = SPRG3;}});
+ 0x269: mfhdar({{Rt = HDAR;}});
+ 0x285: mfdawr0({{ Rt = DAWR0; }});
+ 0x289: mfspurr({{Rt = SPURR;}}, [ IsPrivileged ]);
+ 0x2a9: mfpurr({{Rt = PURR;}}, [ IsPrivileged ]);
0x2C0: mfdec({{ Rt = DEC; }});
+ 0x2c9: mfhdec({{Rt = HDEC;}});
+ 0x2fa: mfpsscr({{Rt = PSSCR;}});
+ 0x324: mffscr({{Rt = FSCR;}});
+ 0x329: mfhrmor({{Rt = HRMOR;}});
0x340: mfsrr0({{ Rt = SRR0; }});
+ 0x345: mfrpr({{ Rt = RPR; }});
+ 0x349: mfhssr0({{Rt = HSRR0;}});
0x360: mfsrr1({{ Rt = SRR1; }});
+ 0x365: mfciabr({{ Rt = CIABR; }});
+ 0x368: mfcir({{Rt = CIR;}}, [ IsPrivileged ]);
+ 0x369: mfhssr1({{Rt = HSRR1;}});
0x380: mfcfar({{ Rt = CFAR; }});
- 0x104: mfctrl({{ Rt = CTRL; }});
- 0x008: mfvrsave({{ Rt = VRSAVE; }});
- 0x1A8: mftbu({{ Rt = TBU; }});
- 0x3E8: mfpvr({{ Rt = PVR; }});
- 0x01C: mfppr({{ Rt = PPR; }});
- 0x05C: mfppr2({{ Rt =PPR32; }});
- 0x20E: mfptcr({{ Rt = PTCR; }});
- 0x208: mfsprg0({{Rt = SPRG0;}});
- 0x228: mfsprg1({{Rt = SPRG1;}});
- 0x248: mfsprg2({{Rt = SPRG2;}});
- 0x268: mfsprg3({{Rt = SPRG3;}});
+ 0x3a0: mfamr({{ Rt = AMR; }}, [ IsPrivileged ]);
+ 0x3a1: mfiamr({{Rt = IAMR;}});
+ 0x3a4: mfuamor({{ Rt = UAMOR; }}, [ IsPrivileged ]);
+ 0x3aa: mfamor({{Rt = AMOR;}});
+ 0x3c5: mfhfscr({{Rt = HFSCR;}});
0x3c9: mflpcr({{Rt = LPCR;}});
- 0x324: mffscr({{Rt = FSCR;}});
- 0x2fa: mfpsscr({{Rt = PSSCR;}});
+ 0x3E8: mfpvr({{ Rt = PVR; }});
0x3e9: mflpidr({{Rt = LPIDR;}});
- 0x3c5: mfhfscr({{Rt = HFSCR;}});
- 0x21f: mfhir0({{Rt = HIR0;}});
- 0x3aa: mfamor({{Rt = AMOR;}});
- 0x3a1: mfiamr({{Rt = IAMR;}});
- 0x369: mfhssr1({{Rt = HSRR1;}});
- 0x349: mfhssr0({{Rt = HSRR0;}});
- 0x2c9: mfhdec({{Rt = HDEC;}});
- 0x24a: mfpcr({{Rt = PCR;}});
+ 0x3ff: mfpir({{ Rt = PIR;}}, [ IsPrivileged ]);
}
467: decode SPR {
- 0x20: mtxer({{ XER = Rs; }});
+ 0x004: mttfhar({{TFHAR = Rs;}});
+ 0x008: mtvrsave({{ VRSAVE = Rs; }});
+ 0x019: mtbescrs({{BESCRS = Rs;}});
+ 0x01C: mtppr({{ PPR = Rs; }});
+ 0x020: mtxer({{ XER = Rs; }});
+ 0x024: mttfiar({{TFIAR = Rs;}});
+ 0x039: mtbescrsu({{BESCRSU = Rs;}});
+ 0x044: mttexasr({{TEXASR = Rs;}});
+ 0x05C: mtppr32({{ PPR32 = Rs; }});
+ 0x078: mtupmc1({{PMC1 = Rs;}});
+ 0x098: mtupmc2({{PMC2 = Rs;}});
+ 0x099: mtebbhr({{EBBHR = Rs;}});
+ 0x0b8: mtupmc3({{PMC3 = Rs;}});
+ 0x0b9: mtebbrr({{EBBRR = Rs;}});
+ 0x0d8: mtupmc4({{PMC4 = Rs;}});
+ 0x0d9: mtbescr({{BESCR = Rs;}});
+ 0x0f8: mtupmc5({{PMC5 = Rs;}});
0x100: mtlr({{ LR = Rs; }});
+ 0x118: mtupmc6({{PMC6 = Rs;}});
0x120: mtctr({{ CTR = Rs; }});
- 0x390: mttbl({{ TBL = Rs; }});
+ 0x1A8: mttbu({{ TBU = Rs; }});
+ 0x1f9: mttar({{TAR = Rs;}});
+ 0x201: mtpidr({{PIDR = Rs;}});
+ 0x204: mttidr({{TIDR = Rs;}}, [ IsPrivileged ]);
+ 0x205: mtdpdes({{DPDES = Rs;}});
+ 0x208: mtsprg0({{SPRG0 = Rs;}});
+ 0x209: mthsprg0({{HSPRG0 = Rs;}});
+ 0x20a: mthmer({{HMER = Rs;}});
+ 0x20E: mtptcr({{ PTCR = Rs; }});
+ 0x219: mtasdr({{ASDR = Rs;}});
+ 0x21a: mtic({{IC = Rs;}});
+ 0x21f: mthir0({{HIR0 = Rs;}});
0x220: mtdscr({{ DSCR = Rs; }});
+ 0x228: mtsprg1({{SPRG1 = Rs;}});
+ 0x229: mthsprg1({{HSPRG1 = Rs;}});
+ 0x22a: mthmeer({{HMEER = Rs;}});
+ 0x238: mtmmcr2({{MMCR2 = Rs;}});
+ 0x23a: mtvtb({{VTB = Rs;}});
0x240: mtdsisr({{ DSISR = Rs; }});
+ 0x248: mtsprg2({{SPRG2 = Rs;}});
+ 0x249: mthdisr({{HDSISR = Rs;}});
+ 0x24a: mtpcr({{PCR = Rs;}});
+ 0x258: mtmmcra({{MMCRA = Rs;}});
0x260: mtdar({{ DAR = Rs; }});
+ 0x268: mtsprg3({{SPRG3 = Rs;}});
+ 0x269: mthdar({{HDAR = Rs;}});
+ 0x27a: mtmmcrc({{MMCRC = Rs;}});
+ 0x285: mtdawr0({{DAWR0 = Rs;}});
+ 0x289: mtspurr({{SPURR = Rs;}});
+ 0x2a9: mtpurr({{PURR = Rs;}});
0x2C0: mtdec({{ DEC = Rs; }});
+ 0x2c9: mthdec({{HDEC = Rs;}});
+ 0x2fa: mtpsscr({{PSSCR = Rs;}});
+ 0x304: mtctrl({{ CTRL = Rs; }});
+ 0x324: mtfscr({{FSCR = Rs;}});
+ 0x329: mthrmor({{HRMOR = Rs;}});
0x340: mtsrr0({{ SRR0 = Rs; }});
+ 0x345: mtrpr({{RPR = Rs;}});
+ 0x349: mthssr0({{HSRR0 = Rs;}});
0x360: mtsrr1({{ SRR1 = Rs; }});
+ 0x365: mtciabr({{CIABR = Rs;}});
+ 0x369: mthssr1({{HSRR1 = Rs;}});
+ 0x378: mtmmcr0({{MMCR0 = Rs;}});
0x380: mtcfar({{ CFAR = Rs; }});
- 0x304: mtctrl({{ CTRL = Rs; }});
- 0x008: mtvrsave({{ VRSAVE = Rs; }});
- 0x1A8: mttbu({{ TBU = Rs; }});
- 0x01C: mtppr({{ PPR = Rs; }});
- 0x05C: mtppr32({{ PPR32 = Rs; }});
- 0x20E: mtptcr({{ PTCR = Rs; }});
- 0x208: mtsprg0({{SPRG0 = Rs;}});
- 0x228: mtsprg1({{SPRG1 = Rs;}});
- 0x248: mtsprg2({{SPRG2 = Rs;}});
- 0x268: mtsprg3({{SPRG3 = Rs;}});
+ 0x390: mttbl({{ TBL = Rs; }});
+ 0x3a0: mtamr({{AMR = Rs;}}, [ IsPrivileged ]);
+ 0x3a1: mtiamr({{IAMR = Rs;}});
+ 0x3a4: mtuamor({{UAMOR = Rs;}}, [ IsPrivileged ]);
+ 0x3aa: mtamor({{AMOR = Rs;}});
+ 0x3c5: mthfscr({{HFSCR = Rs;}});
+ 0x3c8: mttbu40({{TBU40 = Rs;}});
0x3c9: mtlpcr({{LPCR = Rs;}});
- 0x324: mtfscr({{FSCR = Rs;}});
- 0x258: mtmmcra({{MMCRA = Rs;}});
- 0x378: mtmmcr0({{MMCR0 = Rs;}});
0x3d8: mtmmcr1({{MMCR1 = Rs;}});
- 0x238: mtmmcr2({{MMCR2 = Rs;}});
- 0x2fa: mtpsscr({{PSSCR = Rs;}});
0x3e9: mtlpidr({{LPIDR = Rs;}});
- 0x201: mtpidr({{PIDR = Rs;}});
- 0x3c5: mthfscr({{HFSCR = Rs;}});
- 0x27a: mtmmcrc({{MMCRC = Rs;}});
- 0x209: mthsprg0({{HSPRG0 = Rs;}});
- 0x21f: mthir0({{HIR0 = Rs;}});
- 0x3aa: mtamor({{AMOR = Rs;}});
- 0x3a1: mtiamr({{IAMR = Rs;}});
- 0x369: mthssr1({{HSRR1 = Rs;}});
- 0x349: mthssr0({{HSRR0 = Rs;}});
- 0x2c9: mthdec({{HDEC = Rs;}});
- 0x24a: mtpcr({{PCR = Rs;}});
}
- 83: mfmsr({{ Rt = MSR }});
+
+ 83: mfmsr({{ Rt = MSR; }}, [ IsPrivileged ]);
+
178: mtmsrd({{
if (L == 0 ) {
uint64_t val = bits(Rs, 34, 32);
MSR = insertBits(MSR,15,bits(Rs,15));
MSR = insertBits(MSR,1,bits(Rs,1));
}
- }});
+ }}, [ IsPrivileged ]);
}
// Integer logic instructions use source registers Rs and Rb,
759: stfdux({{ Mem_df = Fs; }});
}
+ format MiscOp {
+ 238: msgclr({{
+ ThreadContext *tc = xc->tcBase();
+ ThreadID t = tc->threadId();
+ if(bits(Rb_ud, 31, 27) == 0x5) {
+ tc->getCpuPtr()->clearInterrupt(t, 7, 0);
+ }
+ }});
+
+ 886:msgsync({{ }});
+
+ 206: msgsnd({{
+ if(bits(Rb_ud, 31, 27) == 0x5) {
+ ThreadContext *tc = xc->tcBase();
+
+ //Check for all threads in that processor
+ //to generate Doorbell Interrupt.
+
+ for(ThreadID i = 0; i < tc->getCpuPtr()->numContexts();
+ i++) {
+ if(i != tc->threadId())
+ {
+
+ ThreadContext *t = tc->getCpuPtr()->getContext(i);
+ printf("Read register PIR value %d Thread Id %d\n",
+ (int)t->readIntReg(INTREG_PIR),(int)i);
+ uint32_t val1 = t->readIntReg(INTREG_PIR);
+ printf("Read second register\n");
+ printf("Read register Rb_ud value 0x%016lxThread Id %d\n",
+ Rb_ud,(int)tc->threadId());
+ uint64_t val2 = Rb_ud;
+ printf("Reading done");
+ if(bits(val1, 19, 0) == bits(val2, 19, 0)){
+ printf("Intterupt Happen\n");
+ t->getCpuPtr()->postInterrupt(i, 7, 0);
+ }
+ }
+ }
+ }
+ }});
+
+ 174: msgclrp({{
+ ThreadContext *tc = xc->tcBase();
+ int t = tc->threadId();
+ if(bits(Rb_ud, 31, 27) == 0x5) {
+ DPDES = DPDES & ~(1 << (t - 1));
+ }
+ }}, [ IsPrivileged ]);
+ }
+
// These instructions all provide data cache hints
+ // Right now doesn't have cache support
format MiscOp {
278: dcbt({{ }});
246: dcbtst({{ }});
+
+ 1014: dcbz({{
+ Request::Flags flags = Request::PHYSICAL;
+ Addr EA;
+ if(RA == 0)
+ EA = Rb & -128ULL;
+ else
+ EA = (Ra + Rb) & -128ULL;
+ Mem = 0;
+ for (int i = 0; i < 16; ++i) {
+ writeMemAtomic(xc, traceData, Mem,EA + i*8,
+ flags, NULL);
+ }
+ }});
+
+ 86: dcbf({{ }});
598: sync({{ }}, [ IsMemBarrier ]);
854: eieio({{ }}, [ IsMemBarrier ]);
+ 54: dcbst({{ }});
+ 982: icbi({{ }});
+ 306: tlbie({{ }});
+ 274: tlbiel({{ }}, [ IsPrivileged ]);
+ 566: tlbsync({{ }});
+ 498: slbia({{ }}, [ IsPrivileged ]);
}
// These instructions are of XO form with bit 21 as the OE bit.
projects / gem5.git / blobdiff