arch: cpu: Rename *FloatRegBits* to *FloatReg*.

[gem5.git] / src / arch / power / registers.hh

diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 8b2aefc47114b372c63c3c0ab527d79c2b41f6cc..909c24e9632e8866ce2ce018dd3bd04e4dcbffd1 100644 (file)
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -31,22 +31,44 @@
 #ifndef __ARCH_POWER_REGISTERS_HH__
 #define __ARCH_POWER_REGISTERS_HH__
 
-#include "arch/power/max_inst_regs.hh"
+#include "arch/generic/vec_pred_reg.hh"
+#include "arch/generic/vec_reg.hh"
+#include "arch/power/generated/max_inst_regs.hh"
 #include "arch/power/miscregs.hh"
+#include "base/types.hh"
 
 namespace PowerISA {
 
 using PowerISAInst::MaxInstSrcRegs;
 using PowerISAInst::MaxInstDestRegs;
 
-typedef uint8_t RegIndex;
+// Power writes a misc register outside of the isa parser, so it can't
+// be detected by it. Manually add it here.
+const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
 
-typedef uint64_t IntReg;
+typedef RegVal IntReg;
 
 // Floating point register file entry type
-typedef uint64_t FloatRegBits;
-typedef double FloatReg;
-typedef uint64_t MiscReg;
+typedef RegVal FloatReg;
+typedef RegVal MiscReg;
+
+// dummy typedef since we don't have CC regs
+typedef uint8_t CCReg;
+
+// Not applicable to Power
+using VecElem = ::DummyVecElem;
+using VecReg = ::DummyVecReg;
+using ConstVecReg = ::DummyConstVecReg;
+using VecRegContainer = ::DummyVecRegContainer;
+constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
+constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
+
+// Not applicable to Power
+using VecPredReg = ::DummyVecPredReg;
+using ConstVecPredReg = ::DummyConstVecPredReg;
+using VecPredRegContainer = ::DummyVecPredRegContainer;
+constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
+constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
 
 // Constants Related to the number of registers
 const int NumIntArchRegs = 32;
@@ -60,6 +82,11 @@ const int NumInternalProcRegs = 0;
 
 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
+const int NumVecRegs = 1;  // Not applicable to Power
+                           // (1 to prevent warnings)
+const int NumVecPredRegs = 1;  // Not applicable to Power
+                               // (1 to prevent warnings)
+const int NumCCRegs = 0;
 const int NumMiscRegs = NUM_MISCREGS;
 
 // Semantically meaningful register indices
@@ -79,17 +106,6 @@ const int SyscallNumReg = 0;
 const int SyscallPseudoReturnReg = 3;
 const int SyscallSuccessReg = 3;
 
-// These help enumerate all the registers for dependence tracking.
-const int FP_Base_DepTag = NumIntRegs;
-const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
-const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
-
-typedef union {
-    IntReg   intreg;
-    FloatReg fpreg;
-    MiscReg  ctrlreg;
-} AnyReg;
-
 enum MiscIntRegNums {
     INTREG_CR = NumIntArchRegs,
     INTREG_XER,